From 6a6e8446b97e8a3dfc0984660253b1ac437a445a Mon Sep 17 00:00:00 2001 From: David Wood Date: Sat, 28 Feb 2026 21:24:33 +0000 Subject: [PATCH] intrinsics_data: add sve intrinsics Co-authored-by: Adam Gemmell Co-authored-by: Jamie Cunliffe Co-authored-by: Jacob Bramley Co-authored-by: Luca Vizzarro --- .../intrinsics_data/arm_intrinsics.json | 211216 ++++++++++++++- 1 file changed, 208393 insertions(+), 2823 deletions(-) diff --git a/library/stdarch/intrinsics_data/arm_intrinsics.json b/library/stdarch/intrinsics_data/arm_intrinsics.json index bce85d19a10f..3a3b962a4873 100644 --- a/library/stdarch/intrinsics_data/arm_intrinsics.json +++ b/library/stdarch/intrinsics_data/arm_intrinsics.json @@ -224,21 +224,25 @@ ] }, { - "SIMD_ISA": "Neon", - "name": "vscale_f16", + "SIMD_ISA": "SVE2", + "name": "svaba[_n_s16]", "arguments": [ - "float16x4_t a", - "int16x4_t b" + "svint16_t op1", + "svint16_t op2", + "int16_t op3" ], "return_type": { - "value": "float16x4_t" + "value": "svint16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.4H" + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" } }, "Architectures": [ @@ -246,26 +250,165075 @@ ], "instructions": [ [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_n_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABA" + ], + [ + "MOVPRFX", + "UABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABA" + ], + [ + "MOVPRFX", + "UABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABA" + ], + [ + "MOVPRFX", + "UABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_n_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABA" + ], + [ + "MOVPRFX", + "UABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABA" + ], + [ + "MOVPRFX", + "UABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABA" + ], + [ + "MOVPRFX", + "UABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABA" + ], + [ + "MOVPRFX", + "UABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaba[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABA" + ], + [ + "MOVPRFX", + "UABA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalb[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalb[_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalb[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalb[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABALB" + ], + [ + "MOVPRFX", + "SABALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalb[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalb[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalb[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABALB" + ], + [ + "MOVPRFX", + "UABALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalt[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalt[_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalt[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalt[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABALT" + ], + [ + "MOVPRFX", + "SABALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalt[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalt[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabalt[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABALT" + ], + [ + "MOVPRFX", + "UABALT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABD" + ], + [ + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FABD" + ], + [ + "MOVPRFX", + "FABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABD" + ], + [ + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SABD" + ], + [ + "MOVPRFX", + "SABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABD" + ], + [ + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabd[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UABD" + ], + [ + "MOVPRFX", + "UABD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_s16]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_s32]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_s64]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_u16]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_u32]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlb[_n_u64]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlb[_s16]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlb[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlb[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlb[_u16]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlb[_u32]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlb[_u64]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_s16]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_s32]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_s64]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_u16]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_u32]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlt[_n_u64]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlt[_s16]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlt[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlt[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlt[_u16]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlt[_u32]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svabdlt[_u64]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_f16]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABS" + ], + [ + "MOVPRFX", + "FABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABS" + ], + [ + "MOVPRFX", + "FABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_f32]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABS" + ], + [ + "MOVPRFX", + "FABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABS" + ], + [ + "MOVPRFX", + "FABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_f64]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABS" + ], + [ + "MOVPRFX", + "FABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABS" + ], + [ + "MOVPRFX", + "FABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_s16]_m", + "arguments": [ + "svint16_t inactive", + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ABS" + ], + [ + "MOVPRFX", + "ABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ABS" + ], + [ + "MOVPRFX", + "ABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_s32]_m", + "arguments": [ + "svint32_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ABS" + ], + [ + "MOVPRFX", + "ABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ABS" + ], + [ + "MOVPRFX", + "ABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_s64]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ABS" + ], + [ + "MOVPRFX", + "ABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ABS" + ], + [ + "MOVPRFX", + "ABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_s8]_m", + "arguments": [ + "svint8_t inactive", + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ABS" + ], + [ + "MOVPRFX", + "ABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ABS" + ], + [ + "MOVPRFX", + "ABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svabs[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacge[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacge[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacge[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacge[_n_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacge[_n_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacge[_n_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacgt[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacgt[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacgt[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacgt[_n_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacgt[_n_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacgt[_n_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacle[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacle[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacle[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacle[_n_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacle[_n_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svacle[_n_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaclt[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaclt[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaclt[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaclt[_n_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaclt[_n_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaclt[_n_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADALP" + ], + [ + "MOVPRFX", + "SADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADALP" + ], + [ + "MOVPRFX", + "UADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadalp[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UADALP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadclb[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADCLB" + ], + [ + "MOVPRFX", + "ADCLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadclb[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADCLB" + ], + [ + "MOVPRFX", + "ADCLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadclb[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADCLB" + ], + [ + "MOVPRFX", + "ADCLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadclb[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADCLB" + ], + [ + "MOVPRFX", + "ADCLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadclt[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADCLT" + ], + [ + "MOVPRFX", + "ADCLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadclt[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADCLT" + ], + [ + "MOVPRFX", + "ADCLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadclt[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADCLT" + ], + [ + "MOVPRFX", + "ADCLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svadclt[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADCLT" + ], + [ + "MOVPRFX", + "ADCLT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADD" + ], + [ + "MOVPRFX", + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADD" + ], + [ + "FADD" + ], + [ + "FADD" + ], + [ + "MOVPRFX", + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADD" + ], + [ + "MOVPRFX", + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADD" + ], + [ + "FADD" + ], + [ + "FADD" + ], + [ + "MOVPRFX", + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADD" + ], + [ + "MOVPRFX", + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADD" + ], + [ + "FADD" + ], + [ + "FADD" + ], + [ + "MOVPRFX", + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADD" + ], + [ + "FSUB" + ], + [ + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADD" + ], + [ + "FSUB" + ], + [ + "FADD" + ], + [ + "FADD" + ], + [ + "FADD" + ], + [ + "MOVPRFX", + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FSUB" + ], + [ + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADD" + ], + [ + "FSUB" + ], + [ + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADD" + ], + [ + "FSUB" + ], + [ + "FADD" + ], + [ + "FADD" + ], + [ + "FADD" + ], + [ + "MOVPRFX", + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FSUB" + ], + [ + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADD" + ], + [ + "FSUB" + ], + [ + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADD" + ], + [ + "FSUB" + ], + [ + "FADD" + ], + [ + "FADD" + ], + [ + "FADD" + ], + [ + "MOVPRFX", + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FSUB" + ], + [ + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "SUB" + ], + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADD" + ], + [ + "ADD" + ], + [ + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadd[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ADD" + ], + [ + "MOVPRFX", + "ADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadda[_f16]", + "arguments": [ + "svbool_t pg", + "float16_t initial", + "svfloat16_t op" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "initial": { + "register": "Htied" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADDA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadda[_f32]", + "arguments": [ + "svbool_t pg", + "float32_t initial", + "svfloat32_t op" + ], + "return_type": { + "value": "float32_t" + }, + "Arguments_Preparation": { + "initial": { + "register": "Stied" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADDA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadda[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t initial", + "svfloat64_t op" + ], + "return_type": { + "value": "float64_t" + }, + "Arguments_Preparation": { + "initial": { + "register": "Dtied" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADDA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_s16]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_s32]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_s64]", + "arguments": [ + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnb[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_s16]", + "arguments": [ + "svint8_t even", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_s32]", + "arguments": [ + "svint16_t even", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_s64]", + "arguments": [ + "svint32_t even", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_u16]", + "arguments": [ + "svuint8_t even", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_u32]", + "arguments": [ + "svuint16_t even", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_n_u64]", + "arguments": [ + "svuint32_t even", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_s16]", + "arguments": [ + "svint8_t even", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_s32]", + "arguments": [ + "svint16_t even", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_s64]", + "arguments": [ + "svint32_t even", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_u16]", + "arguments": [ + "svuint8_t even", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_u32]", + "arguments": [ + "svuint16_t even", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddhnt[_u64]", + "arguments": [ + "svuint32_t even", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_s16]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_s32]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_s64]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_u16]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_u32]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlb[_n_u64]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlb[_s16]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlb[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlb[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlb[_u16]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlb[_u32]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlb[_u64]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_n_s16]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_n_s32]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_n_s64]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_s16]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlbt[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_s16]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_s32]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_s64]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_u16]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_u32]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlt[_n_u64]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlt[_s16]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlt[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlt[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlt[_u16]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlt[_u32]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddlt[_u64]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADDP" + ], + [ + "MOVPRFX", + "FADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddp[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADDP" + ], + [ + "MOVPRFX", + "ADDP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaddv[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaddv[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "float32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaddv[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "float64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaddv[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaddv[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaddv[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaddv[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaddv[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaddv[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaddv[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svaddv[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDV" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_s16]", + "arguments": [ + "svint16_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_s32]", + "arguments": [ + "svint32_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_s64]", + "arguments": [ + "svint64_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwb[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwb[_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwb[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwb[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwb[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwb[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwb[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_s16]", + "arguments": [ + "svint16_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_s32]", + "arguments": [ + "svint32_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_s64]", + "arguments": [ + "svint64_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwt[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwt[_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwt[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwt[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SADDWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwt[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwt[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaddwt[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UADDWT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadrb[_u32base]_[s32]offset", + "arguments": [ + "svuint32_t bases", + "svint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offsets": { + "register": "Zoffsets.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadrb[_u32base]_[u32]offset", + "arguments": [ + "svuint32_t bases", + "svuint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offsets": { + "register": "Zoffsets.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadrb[_u64base]_[s64]offset", + "arguments": [ + "svuint64_t bases", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offsets": { + "register": "Zoffsets.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadrb[_u64base]_[u64]offset", + "arguments": [ + "svuint64_t bases", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offsets": { + "register": "Zoffsets.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadrd[_u32base]_[s32]index", + "arguments": [ + "svuint32_t bases", + "svint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadrd[_u32base]_[u32]index", + "arguments": [ + "svuint32_t bases", + "svuint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadrd[_u64base]_[s64]index", + "arguments": [ + "svuint64_t bases", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadrd[_u64base]_[u64]index", + "arguments": [ + "svuint64_t bases", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadrh[_u32base]_[s32]index", + "arguments": [ + "svuint32_t bases", + "svint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadrh[_u32base]_[u32]index", + "arguments": [ + "svuint32_t bases", + "svuint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadrh[_u64base]_[s64]index", + "arguments": [ + "svuint64_t bases", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadrh[_u64base]_[u64]index", + "arguments": [ + "svuint64_t bases", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadrw[_u32base]_[s32]index", + "arguments": [ + "svuint32_t bases", + "svint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadrw[_u32base]_[u32]index", + "arguments": [ + "svuint32_t bases", + "svuint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "indices": { + "register": "Zindices.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadrw[_u64base]_[s64]index", + "arguments": [ + "svuint64_t bases", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svadrw[_u64base]_[u64]index", + "arguments": [ + "svuint64_t bases", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "indices": { + "register": "Zindices.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ADR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaesd[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AESD" + ], + [ + "AESD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaese[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AESE" + ], + [ + "AESE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaesimc[_u8]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Ztied.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AESIMC" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svaesmc[_u8]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Ztied.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AESMC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_b]_z", + "arguments": [ + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTB" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTB" + ], + [ + "UXTH" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "UXTH" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTB" + ], + [ + "UXTH" + ], + [ + "UXTW" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "UXTH" + ], + [ + "MOVPRFX", + "UXTW" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTB" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTB" + ], + [ + "UXTH" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "UXTH" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTB" + ], + [ + "UXTH" + ], + [ + "UXTW" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UXTB" + ], + [ + "MOVPRFX", + "UXTH" + ], + [ + "MOVPRFX", + "UXTW" + ], + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "AND" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svand[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "AND" + ], + [ + "MOVPRFX", + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svandv[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ANDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svandv[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ANDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svandv[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ANDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svandv[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "int8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ANDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svandv[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ANDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svandv[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ANDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svandv[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ANDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svandv[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "uint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ANDV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASRR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASRR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ], + [ + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ], + [ + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ], + [ + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASR" + ], + [ + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasr_wide[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASRD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASRD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Zop1.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASRD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ASRD" + ], + [ + "MOVPRFX", + "ASRD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svasrd[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ASRD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbcax[_n_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbcax[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbcax[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbcax[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbcax[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbcax[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbcax[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbcax[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbcax[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BCAX" + ], + [ + "MOVPRFX", + "BCAX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbdep[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BDEP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbdep[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BDEP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbdep[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BDEP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbdep[_n_u8]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BDEP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbdep[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BDEP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbdep[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BDEP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbdep[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BDEP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbdep[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BDEP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbext[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbext[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbext[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbext[_n_u8]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbext[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbext[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbext[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbext[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbgrp[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BGRP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbgrp[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BGRP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbgrp[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BGRP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbgrp[_n_u8]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BGRP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbgrp[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BGRP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbgrp[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BGRP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbgrp[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BGRP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbgrp[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BGRP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_b]_z", + "arguments": [ + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "BIC" + ], + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "BIC" + ], + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "BIC" + ], + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "BIC" + ], + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "BIC" + ], + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "BIC" + ], + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "BIC" + ], + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ], + [ + "BIC" + ], + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BIC" + ], + [ + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbic[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "BIC" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbrka[_b]_m", + "arguments": [ + "svbool_t inactive", + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Ptied.B" + }, + "op": { + "register": "Pop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BRKA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbrka[_b]_z", + "arguments": [ + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Pop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BRKA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbrkb[_b]_m", + "arguments": [ + "svbool_t inactive", + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Ptied.B" + }, + "op": { + "register": "Pop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BRKB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbrkb[_b]_z", + "arguments": [ + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Pop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BRKB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbrkn[_b]_z", + "arguments": [ + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Ptied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BRKN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbrkpa[_b]_z", + "arguments": [ + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BRKPA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svbrkpb[_b]_z", + "arguments": [ + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BRKPB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_n_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl1n[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL1N" + ], + [ + "MOVPRFX", + "BSL1N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_n_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl2n[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL2N" + ], + [ + "MOVPRFX", + "BSL2N" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL" + ], + [ + "MOVPRFX", + "BSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL" + ], + [ + "MOVPRFX", + "BSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL" + ], + [ + "MOVPRFX", + "BSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL" + ], + [ + "MOVPRFX", + "BSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL" + ], + [ + "MOVPRFX", + "BSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL" + ], + [ + "MOVPRFX", + "BSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL" + ], + [ + "MOVPRFX", + "BSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl[_n_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL" + ], + [ + "MOVPRFX", + "BSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL" + ], + [ + "MOVPRFX", + "BSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL" + ], + [ + "MOVPRFX", + "BSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL" + ], + [ + "MOVPRFX", + "BSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL" + ], + [ + "MOVPRFX", + "BSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL" + ], + [ + "MOVPRFX", + "BSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL" + ], + [ + "MOVPRFX", + "BSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL" + ], + [ + "MOVPRFX", + "BSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svbsl[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "BSL" + ], + [ + "MOVPRFX", + "BSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcadd[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcadd[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcadd[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcadd[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcadd[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcadd[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcadd[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcadd[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCADD" + ], + [ + "MOVPRFX", + "FCADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcadd[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcadd[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CADD" + ], + [ + "MOVPRFX", + "CADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcadd[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CADD" + ], + [ + "MOVPRFX", + "CADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcadd[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CADD" + ], + [ + "MOVPRFX", + "CADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcadd[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CADD" + ], + [ + "MOVPRFX", + "CADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcadd[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CADD" + ], + [ + "MOVPRFX", + "CADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcadd[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CADD" + ], + [ + "MOVPRFX", + "CADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcadd[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CADD" + ], + [ + "MOVPRFX", + "CADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcadd[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CADD" + ], + [ + "MOVPRFX", + "CADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcdot[_s32]", + "arguments": [ + "svint32_t op1", + "svint8_t op2", + "svint8_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CDOT" + ], + [ + "MOVPRFX", + "CDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcdot[_s64]", + "arguments": [ + "svint64_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CDOT" + ], + [ + "MOVPRFX", + "CDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcdot_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint8_t op2", + "svint8_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CDOT" + ], + [ + "MOVPRFX", + "CDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcdot_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CDOT" + ], + [ + "MOVPRFX", + "CDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svclamp[_f16]", + "arguments": [ + "svfloat16_t op", + "svfloat16_t min", + "svfloat16_t max" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "max": { + "register": "Zreg3.H" + }, + "min": { + "register": "Zreg2.H" + }, + "op": { + "register": "Zreg1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCLAMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svclamp[_f32]", + "arguments": [ + "svfloat32_t op", + "svfloat32_t min", + "svfloat32_t max" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "max": { + "register": "Zreg3.S" + }, + "min": { + "register": "Zreg2.S" + }, + "op": { + "register": "Zreg1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCLAMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svclamp[_f64]", + "arguments": [ + "svfloat64_t op", + "svfloat64_t min", + "svfloat64_t max" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "max": { + "register": "Zreg3.D" + }, + "min": { + "register": "Zreg2.D" + }, + "op": { + "register": "Zreg1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCLAMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svclamp[_s16]", + "arguments": [ + "svint16_t op", + "svint16_t min", + "svint16_t max" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "max": { + "register": "Zreg3.H" + }, + "min": { + "register": "Zreg2.H" + }, + "op": { + "register": "Zreg1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCLAMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svclamp[_s32]", + "arguments": [ + "svint32_t op", + "svint32_t min", + "svint32_t max" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "max": { + "register": "Zreg3.S" + }, + "min": { + "register": "Zreg2.S" + }, + "op": { + "register": "Zreg1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCLAMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svclamp[_s64]", + "arguments": [ + "svint64_t op", + "svint64_t min", + "svint64_t max" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "max": { + "register": "Zreg3.D" + }, + "min": { + "register": "Zreg2.D" + }, + "op": { + "register": "Zreg1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCLAMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svclamp[_s8]", + "arguments": [ + "svint8_t op", + "svint8_t min", + "svint8_t max" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "max": { + "register": "Zreg3.B" + }, + "min": { + "register": "Zreg2.B" + }, + "op": { + "register": "Zreg1.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCLAMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svclamp[_u16]", + "arguments": [ + "svuint16_t op", + "svuint16_t min", + "svuint16_t max" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "max": { + "register": "Zreg3.H" + }, + "min": { + "register": "Zreg2.H" + }, + "op": { + "register": "Zreg1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCLAMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svclamp[_u32]", + "arguments": [ + "svuint32_t op", + "svuint32_t min", + "svuint32_t max" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "max": { + "register": "Zreg3.S" + }, + "min": { + "register": "Zreg2.S" + }, + "op": { + "register": "Zreg1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCLAMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svclamp[_u64]", + "arguments": [ + "svuint64_t op", + "svuint64_t min", + "svuint64_t max" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "max": { + "register": "Zreg3.D" + }, + "min": { + "register": "Zreg2.D" + }, + "op": { + "register": "Zreg1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCLAMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svclamp[_u8]", + "arguments": [ + "svuint8_t op", + "svuint8_t min", + "svuint8_t max" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "max": { + "register": "Zreg3.B" + }, + "min": { + "register": "Zreg2.B" + }, + "op": { + "register": "Zreg1.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCLAMP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t fallback", + "svfloat16_t data" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t fallback", + "svfloat32_t data" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t fallback", + "svfloat64_t data" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_n_f16]", + "arguments": [ + "svbool_t pg", + "float16_t fallback", + "svfloat16_t data" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_n_f32]", + "arguments": [ + "svbool_t pg", + "float32_t fallback", + "svfloat32_t data" + ], + "return_type": { + "value": "float32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_n_f64]", + "arguments": [ + "svbool_t pg", + "float64_t fallback", + "svfloat64_t data" + ], + "return_type": { + "value": "float64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_n_s16]", + "arguments": [ + "svbool_t pg", + "int16_t fallback", + "svint16_t data" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_n_s32]", + "arguments": [ + "svbool_t pg", + "int32_t fallback", + "svint32_t data" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_n_s64]", + "arguments": [ + "svbool_t pg", + "int64_t fallback", + "svint64_t data" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_n_s8]", + "arguments": [ + "svbool_t pg", + "int8_t fallback", + "svint8_t data" + ], + "return_type": { + "value": "int8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Btied|Wtied" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_n_u16]", + "arguments": [ + "svbool_t pg", + "uint16_t fallback", + "svuint16_t data" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_n_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t fallback", + "svuint32_t data" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_n_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t fallback", + "svuint64_t data" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_n_u8]", + "arguments": [ + "svbool_t pg", + "uint8_t fallback", + "svuint8_t data" + ], + "return_type": { + "value": "uint8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Btied|Wtied" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t fallback", + "svint16_t data" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t fallback", + "svint32_t data" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t fallback", + "svint64_t data" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t fallback", + "svint8_t data" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Zfallback.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t fallback", + "svuint16_t data" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t fallback", + "svuint32_t data" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t fallback", + "svuint64_t data" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclasta[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t fallback", + "svuint8_t data" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Zfallback.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTA" + ], + [ + "MOVPRFX", + "CLASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t fallback", + "svfloat16_t data" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t fallback", + "svfloat32_t data" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t fallback", + "svfloat64_t data" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_n_f16]", + "arguments": [ + "svbool_t pg", + "float16_t fallback", + "svfloat16_t data" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_n_f32]", + "arguments": [ + "svbool_t pg", + "float32_t fallback", + "svfloat32_t data" + ], + "return_type": { + "value": "float32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_n_f64]", + "arguments": [ + "svbool_t pg", + "float64_t fallback", + "svfloat64_t data" + ], + "return_type": { + "value": "float64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_n_s16]", + "arguments": [ + "svbool_t pg", + "int16_t fallback", + "svint16_t data" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_n_s32]", + "arguments": [ + "svbool_t pg", + "int32_t fallback", + "svint32_t data" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_n_s64]", + "arguments": [ + "svbool_t pg", + "int64_t fallback", + "svint64_t data" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_n_s8]", + "arguments": [ + "svbool_t pg", + "int8_t fallback", + "svint8_t data" + ], + "return_type": { + "value": "int8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Btied|Wtied" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_n_u16]", + "arguments": [ + "svbool_t pg", + "uint16_t fallback", + "svuint16_t data" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Htied|Wtied" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_n_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t fallback", + "svuint32_t data" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Stied|Wtied" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_n_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t fallback", + "svuint64_t data" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Dtied|Xtied" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_n_u8]", + "arguments": [ + "svbool_t pg", + "uint8_t fallback", + "svuint8_t data" + ], + "return_type": { + "value": "uint8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Btied|Wtied" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t fallback", + "svint16_t data" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t fallback", + "svint32_t data" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t fallback", + "svint64_t data" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t fallback", + "svint8_t data" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Zfallback.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t fallback", + "svuint16_t data" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Zfallback.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t fallback", + "svuint32_t data" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Zfallback.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t fallback", + "svuint64_t data" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Zfallback.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclastb[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t fallback", + "svuint8_t data" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Zfallback.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLASTB" + ], + [ + "MOVPRFX", + "CLASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcls[_s16]_m", + "arguments": [ + "svuint16_t inactive", + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLS" + ], + [ + "MOVPRFX", + "CLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcls[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLS" + ], + [ + "MOVPRFX", + "CLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcls[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcls[_s32]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLS" + ], + [ + "MOVPRFX", + "CLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcls[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLS" + ], + [ + "MOVPRFX", + "CLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcls[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcls[_s64]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLS" + ], + [ + "MOVPRFX", + "CLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcls[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLS" + ], + [ + "MOVPRFX", + "CLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcls[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcls[_s8]_m", + "arguments": [ + "svuint8_t inactive", + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLS" + ], + [ + "MOVPRFX", + "CLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcls[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLS" + ], + [ + "MOVPRFX", + "CLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcls[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_s16]_m", + "arguments": [ + "svuint16_t inactive", + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_s32]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_s64]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_s8]_m", + "arguments": [ + "svuint8_t inactive", + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_u16]_m", + "arguments": [ + "svuint16_t inactive", + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_u32]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_u64]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_u8]_m", + "arguments": [ + "svuint8_t inactive", + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CLZ" + ], + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svclz[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CLZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmla[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmla[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmla[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmla[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmla[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmla[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmla[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmla[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmla[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcmla[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcmla[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcmla[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "svint64_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcmla[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "svint8_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcmla[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcmla[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcmla[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcmla[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmla_lane[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmla_lane[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMLA" + ], + [ + "MOVPRFX", + "FCMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcmla_lane[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcmla_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcmla_lane[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcmla_lane[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMLA" + ], + [ + "MOVPRFX", + "CMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMEQ" + ], + [ + "FCMEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMEQ" + ], + [ + "FCMEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMEQ" + ], + [ + "FCMEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ], + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ], + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ], + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ], + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ], + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ], + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ], + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_n_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ], + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_n_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ], + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_n_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ], + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_n_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ], + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpeq_wide[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPEQ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGE" + ], + [ + "FCMGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGE" + ], + [ + "FCMGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGE" + ], + [ + "FCMGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ], + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ], + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ], + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ], + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ], + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ], + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ], + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_n_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ], + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ], + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ], + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ], + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ], + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ], + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_n_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ], + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpge_wide[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGT" + ], + [ + "FCMGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGT" + ], + [ + "FCMGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGT" + ], + [ + "FCMGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ], + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ], + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ], + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ], + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ], + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ], + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ], + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_n_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ], + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ], + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ], + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ], + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ], + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ], + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_n_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ], + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpgt_wide[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_n_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMLE" + ], + [ + "FCMGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_n_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMLE" + ], + [ + "FCMGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_n_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMLE" + ], + [ + "FCMGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_n_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLE" + ], + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_n_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLE" + ], + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_n_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLE" + ], + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_n_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLE" + ], + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_n_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLS" + ], + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_n_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLS" + ], + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_n_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLS" + ], + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_n_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLS" + ], + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLE" + ], + [ + "CMPLE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLE" + ], + [ + "CMPLE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLE" + ], + [ + "CMPLE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLS" + ], + [ + "CMPLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLS" + ], + [ + "CMPLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_n_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLS" + ], + [ + "CMPLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmple_wide[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMLT" + ], + [ + "FCMGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMLT" + ], + [ + "FCMGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMLT" + ], + [ + "FCMGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLT" + ], + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLT" + ], + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLT" + ], + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLT" + ], + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLO" + ], + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLO" + ], + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLO" + ], + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_n_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLO" + ], + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPGT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLT" + ], + [ + "CMPLT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLT" + ], + [ + "CMPLT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLT" + ], + [ + "CMPLT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLO" + ], + [ + "CMPLO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLO" + ], + [ + "CMPLO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_n_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLO" + ], + [ + "CMPLO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmplt_wide[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPLO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMNE" + ], + [ + "FCMNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMNE" + ], + [ + "FCMNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMNE" + ], + [ + "FCMNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ], + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ], + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ], + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ], + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ], + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ], + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ], + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_n_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ], + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_n_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ], + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_n_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ], + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_n_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ], + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpne_wide[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CMPNE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpuo[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMUO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpuo[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMUO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpuo[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMUO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpuo[_n_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMUO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpuo[_n_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMUO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcmpuo[_n_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMUO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_s16]_m", + "arguments": [ + "svint16_t inactive", + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_s32]_m", + "arguments": [ + "svint32_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_s64]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_s8]_m", + "arguments": [ + "svint8_t inactive", + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_u16]_m", + "arguments": [ + "svuint16_t inactive", + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_u32]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_u64]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_u8]_m", + "arguments": [ + "svuint8_t inactive", + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNOT" + ], + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnot[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_f16]_m", + "arguments": [ + "svuint16_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_f32]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_f64]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_s16]_m", + "arguments": [ + "svuint16_t inactive", + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_s32]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_s64]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_s8]_m", + "arguments": [ + "svuint8_t inactive", + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_u16]_m", + "arguments": [ + "svuint16_t inactive", + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_u32]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_u64]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_u8]_m", + "arguments": [ + "svuint8_t inactive", + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNT" + ], + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnt[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "CNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcntb", + "arguments": [], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcntb_pat", + "arguments": [ + "enum svpattern pattern" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcntd", + "arguments": [], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcntd_pat", + "arguments": [ + "enum svpattern pattern" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnth", + "arguments": [], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcnth_pat", + "arguments": [ + "enum svpattern pattern" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcntp_b16", + "arguments": [ + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Pop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcntp_b32", + "arguments": [ + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Pop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcntp_b64", + "arguments": [ + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Pop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcntp_b8", + "arguments": [ + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Pop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcntp_c16", + "arguments": [ + "svcount_t pnn", + "uint64_t vl" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "pnn": { + "register": "PNreg1.H" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcntp_c32", + "arguments": [ + "svcount_t pnn", + "uint64_t vl" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "pnn": { + "register": "PNreg1.S" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcntp_c64", + "arguments": [ + "svcount_t pnn", + "uint64_t vl" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "pnn": { + "register": "PNreg1.D" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcntp_c8", + "arguments": [ + "svcount_t pnn", + "uint64_t vl" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "pnn": { + "register": "PNreg1.B" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcntw", + "arguments": [], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcntw_pat", + "arguments": [ + "enum svpattern pattern" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcompact[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "COMPACT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcompact[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "COMPACT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcompact[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "COMPACT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcompact[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "COMPACT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcompact[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "COMPACT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcompact[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "COMPACT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcreate2[_b]", + "arguments": [ + "svbool_t x", + "svbool_t y" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate2[_f16]", + "arguments": [ + "svfloat16_t x0", + "svfloat16_t x1" + ], + "return_type": { + "value": "svfloat16x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate2[_f32]", + "arguments": [ + "svfloat32_t x0", + "svfloat32_t x1" + ], + "return_type": { + "value": "svfloat32x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate2[_f64]", + "arguments": [ + "svfloat64_t x0", + "svfloat64_t x1" + ], + "return_type": { + "value": "svfloat64x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate2[_s16]", + "arguments": [ + "svint16_t x0", + "svint16_t x1" + ], + "return_type": { + "value": "svint16x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate2[_s32]", + "arguments": [ + "svint32_t x0", + "svint32_t x1" + ], + "return_type": { + "value": "svint32x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate2[_s64]", + "arguments": [ + "svint64_t x0", + "svint64_t x1" + ], + "return_type": { + "value": "svint64x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate2[_s8]", + "arguments": [ + "svint8_t x0", + "svint8_t x1" + ], + "return_type": { + "value": "svint8x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate2[_u16]", + "arguments": [ + "svuint16_t x0", + "svuint16_t x1" + ], + "return_type": { + "value": "svuint16x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate2[_u32]", + "arguments": [ + "svuint32_t x0", + "svuint32_t x1" + ], + "return_type": { + "value": "svuint32x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate2[_u64]", + "arguments": [ + "svuint64_t x0", + "svuint64_t x1" + ], + "return_type": { + "value": "svuint64x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate2[_u8]", + "arguments": [ + "svuint8_t x0", + "svuint8_t x1" + ], + "return_type": { + "value": "svuint8x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate3[_f16]", + "arguments": [ + "svfloat16_t x0", + "svfloat16_t x1", + "svfloat16_t x2" + ], + "return_type": { + "value": "svfloat16x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate3[_f32]", + "arguments": [ + "svfloat32_t x0", + "svfloat32_t x1", + "svfloat32_t x2" + ], + "return_type": { + "value": "svfloat32x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate3[_f64]", + "arguments": [ + "svfloat64_t x0", + "svfloat64_t x1", + "svfloat64_t x2" + ], + "return_type": { + "value": "svfloat64x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate3[_s16]", + "arguments": [ + "svint16_t x0", + "svint16_t x1", + "svint16_t x2" + ], + "return_type": { + "value": "svint16x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate3[_s32]", + "arguments": [ + "svint32_t x0", + "svint32_t x1", + "svint32_t x2" + ], + "return_type": { + "value": "svint32x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate3[_s64]", + "arguments": [ + "svint64_t x0", + "svint64_t x1", + "svint64_t x2" + ], + "return_type": { + "value": "svint64x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate3[_s8]", + "arguments": [ + "svint8_t x0", + "svint8_t x1", + "svint8_t x2" + ], + "return_type": { + "value": "svint8x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate3[_u16]", + "arguments": [ + "svuint16_t x0", + "svuint16_t x1", + "svuint16_t x2" + ], + "return_type": { + "value": "svuint16x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate3[_u32]", + "arguments": [ + "svuint32_t x0", + "svuint32_t x1", + "svuint32_t x2" + ], + "return_type": { + "value": "svuint32x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate3[_u64]", + "arguments": [ + "svuint64_t x0", + "svuint64_t x1", + "svuint64_t x2" + ], + "return_type": { + "value": "svuint64x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate3[_u8]", + "arguments": [ + "svuint8_t x0", + "svuint8_t x1", + "svuint8_t x2" + ], + "return_type": { + "value": "svuint8x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcreate4[_b]", + "arguments": [ + "svbool_t x", + "svbool_t y", + "svbool_t z", + "svbool_t w" + ], + "return_type": { + "value": "svboolx4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate4[_f16]", + "arguments": [ + "svfloat16_t x0", + "svfloat16_t x1", + "svfloat16_t x2", + "svfloat16_t x3" + ], + "return_type": { + "value": "svfloat16x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate4[_f32]", + "arguments": [ + "svfloat32_t x0", + "svfloat32_t x1", + "svfloat32_t x2", + "svfloat32_t x3" + ], + "return_type": { + "value": "svfloat32x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate4[_f64]", + "arguments": [ + "svfloat64_t x0", + "svfloat64_t x1", + "svfloat64_t x2", + "svfloat64_t x3" + ], + "return_type": { + "value": "svfloat64x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate4[_s16]", + "arguments": [ + "svint16_t x0", + "svint16_t x1", + "svint16_t x2", + "svint16_t x3" + ], + "return_type": { + "value": "svint16x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate4[_s32]", + "arguments": [ + "svint32_t x0", + "svint32_t x1", + "svint32_t x2", + "svint32_t x3" + ], + "return_type": { + "value": "svint32x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate4[_s64]", + "arguments": [ + "svint64_t x0", + "svint64_t x1", + "svint64_t x2", + "svint64_t x3" + ], + "return_type": { + "value": "svint64x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate4[_s8]", + "arguments": [ + "svint8_t x0", + "svint8_t x1", + "svint8_t x2", + "svint8_t x3" + ], + "return_type": { + "value": "svint8x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate4[_u16]", + "arguments": [ + "svuint16_t x0", + "svuint16_t x1", + "svuint16_t x2", + "svuint16_t x3" + ], + "return_type": { + "value": "svuint16x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate4[_u32]", + "arguments": [ + "svuint32_t x0", + "svuint32_t x1", + "svuint32_t x2", + "svuint32_t x3" + ], + "return_type": { + "value": "svuint32x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate4[_u64]", + "arguments": [ + "svuint64_t x0", + "svuint64_t x1", + "svuint64_t x2", + "svuint64_t x3" + ], + "return_type": { + "value": "svuint64x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcreate4[_u8]", + "arguments": [ + "svuint8_t x0", + "svuint8_t x1", + "svuint8_t x2", + "svuint8_t x3" + ], + "return_type": { + "value": "svuint8x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_f32]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVT" + ], + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVT" + ], + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_f64]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVT" + ], + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVT" + ], + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_s16]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ], + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ], + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_s32]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ], + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ], + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_s64]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ], + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ], + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_u16]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ], + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ], + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_u32]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ], + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ], + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_u64]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ], + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ], + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f16[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_f16]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVT" + ], + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVT" + ], + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_f64]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVT" + ], + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVT" + ], + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_s32]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ], + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ], + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_s64]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ], + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ], + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_u32]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ], + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ], + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_u64]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ], + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ], + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f32[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_f16]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVT" + ], + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVT" + ], + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_f32]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVT" + ], + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVT" + ], + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_s32]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ], + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ], + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_s64]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ], + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ], + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_u32]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ], + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ], + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_u64]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ], + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ], + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_f64[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s16[_f16]_m", + "arguments": [ + "svint16_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ], + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s16[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ], + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s16[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s32[_f16]_m", + "arguments": [ + "svint32_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ], + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s32[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ], + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s32[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s32[_f32]_m", + "arguments": [ + "svint32_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ], + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s32[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ], + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s32[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s32[_f64]_m", + "arguments": [ + "svint32_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ], + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s32[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ], + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s32[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s64[_f16]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ], + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s64[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ], + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s64[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s64[_f32]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ], + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s64[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ], + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s64[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s64[_f64]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ], + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s64[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ], + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_s64[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u16[_f16]_m", + "arguments": [ + "svuint16_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ], + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u16[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ], + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u16[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u32[_f16]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ], + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u32[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ], + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u32[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u32[_f32]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ], + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u32[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ], + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u32[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u32[_f64]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ], + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u32[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ], + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u32[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u64[_f16]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ], + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u64[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ], + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u64[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u64[_f32]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ], + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u64[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ], + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u64[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u64[_f64]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ], + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u64[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ], + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svcvt_u64[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcvtlt_f32[_f16]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Ztied.S" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcvtlt_f32[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Ztied.H" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcvtlt_f64[_f32]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Ztied.D" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcvtlt_f64[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Ztied.S" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcvtnt_f16[_f32]_m", + "arguments": [ + "svfloat16_t even", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcvtnt_f16[_f32]_x", + "arguments": [ + "svfloat16_t even", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcvtnt_f32[_f64]_m", + "arguments": [ + "svfloat32_t even", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcvtnt_f32[_f64]_x", + "arguments": [ + "svfloat32_t even", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcvtx_f32[_f64]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTX" + ], + [ + "MOVPRFX", + "FCVTX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcvtx_f32[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTX" + ], + [ + "MOVPRFX", + "FCVTX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcvtx_f32[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FCVTX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcvtxnt_f32[_f64]_m", + "arguments": [ + "svfloat32_t even", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTXNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svcvtxnt_f32[_f64]_x", + "arguments": [ + "svfloat32_t even", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTXNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIV" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIV" + ], + [ + "FDIVR" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FDIV" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIV" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIV" + ], + [ + "FDIVR" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FDIV" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIV" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIV" + ], + [ + "FDIVR" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FDIV" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIV" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIV" + ], + [ + "FDIVR" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FDIV" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIV" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIV" + ], + [ + "FDIVR" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FDIV" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIV" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIV" + ], + [ + "FDIVR" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FDIV" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDIV" + ], + [ + "MOVPRFX", + "SDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDIV" + ], + [ + "SDIVR" + ], + [ + "MOVPRFX", + "SDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SDIV" + ], + [ + "MOVPRFX", + "SDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDIV" + ], + [ + "MOVPRFX", + "SDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDIV" + ], + [ + "SDIVR" + ], + [ + "MOVPRFX", + "SDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SDIV" + ], + [ + "MOVPRFX", + "SDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDIV" + ], + [ + "MOVPRFX", + "UDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDIV" + ], + [ + "UDIVR" + ], + [ + "MOVPRFX", + "UDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UDIV" + ], + [ + "MOVPRFX", + "UDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDIV" + ], + [ + "MOVPRFX", + "UDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDIV" + ], + [ + "UDIVR" + ], + [ + "MOVPRFX", + "UDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UDIV" + ], + [ + "MOVPRFX", + "UDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDIV" + ], + [ + "MOVPRFX", + "SDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDIV" + ], + [ + "SDIVR" + ], + [ + "MOVPRFX", + "SDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SDIV" + ], + [ + "MOVPRFX", + "SDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDIV" + ], + [ + "MOVPRFX", + "SDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDIV" + ], + [ + "SDIVR" + ], + [ + "MOVPRFX", + "SDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SDIV" + ], + [ + "MOVPRFX", + "SDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDIV" + ], + [ + "MOVPRFX", + "UDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDIV" + ], + [ + "UDIVR" + ], + [ + "MOVPRFX", + "UDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UDIV" + ], + [ + "MOVPRFX", + "UDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDIV" + ], + [ + "MOVPRFX", + "UDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDIV" + ], + [ + "UDIVR" + ], + [ + "MOVPRFX", + "UDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdiv[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UDIV" + ], + [ + "MOVPRFX", + "UDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIVR" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIVR" + ], + [ + "FDIV" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FDIVR" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIVR" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIVR" + ], + [ + "FDIV" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FDIVR" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIVR" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIVR" + ], + [ + "FDIV" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FDIVR" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIVR" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIVR" + ], + [ + "FDIV" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FDIVR" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIVR" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIVR" + ], + [ + "FDIV" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FDIVR" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIVR" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIVR" + ], + [ + "FDIV" + ], + [ + "MOVPRFX", + "FDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FDIVR" + ], + [ + "MOVPRFX", + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDIVR" + ], + [ + "MOVPRFX", + "SDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDIVR" + ], + [ + "SDIV" + ], + [ + "MOVPRFX", + "SDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SDIVR" + ], + [ + "MOVPRFX", + "SDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDIVR" + ], + [ + "MOVPRFX", + "SDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDIVR" + ], + [ + "SDIV" + ], + [ + "MOVPRFX", + "SDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SDIVR" + ], + [ + "MOVPRFX", + "SDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDIVR" + ], + [ + "MOVPRFX", + "UDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDIVR" + ], + [ + "UDIV" + ], + [ + "MOVPRFX", + "UDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UDIVR" + ], + [ + "MOVPRFX", + "UDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDIVR" + ], + [ + "MOVPRFX", + "UDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDIVR" + ], + [ + "UDIV" + ], + [ + "MOVPRFX", + "UDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UDIVR" + ], + [ + "MOVPRFX", + "UDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDIVR" + ], + [ + "MOVPRFX", + "SDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDIVR" + ], + [ + "SDIV" + ], + [ + "MOVPRFX", + "SDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SDIVR" + ], + [ + "MOVPRFX", + "SDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDIVR" + ], + [ + "MOVPRFX", + "SDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDIVR" + ], + [ + "SDIV" + ], + [ + "MOVPRFX", + "SDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SDIVR" + ], + [ + "MOVPRFX", + "SDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDIVR" + ], + [ + "MOVPRFX", + "UDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDIVR" + ], + [ + "UDIV" + ], + [ + "MOVPRFX", + "UDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UDIVR" + ], + [ + "MOVPRFX", + "UDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDIVR" + ], + [ + "MOVPRFX", + "UDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDIVR" + ], + [ + "UDIV" + ], + [ + "MOVPRFX", + "UDIVR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdivr[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UDIVR" + ], + [ + "MOVPRFX", + "UDIV" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svdot[_f32_f16]", + "arguments": [ + "svfloat32_t zda", + "svfloat16_t zn", + "svfloat16_t zm" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "zda": { + "register": "Zreg1.S" + }, + "zm": { + "register": "Zreg3.H" + }, + "zn": { + "register": "Zreg2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdot[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDOT" + ], + [ + "MOVPRFX", + "SDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdot[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDOT" + ], + [ + "MOVPRFX", + "SDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdot[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDOT" + ], + [ + "MOVPRFX", + "UDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdot[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDOT" + ], + [ + "MOVPRFX", + "UDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdot[_s32]", + "arguments": [ + "svint32_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDOT" + ], + [ + "MOVPRFX", + "SDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svdot[_s32_s16]", + "arguments": [ + "svint32_t zda", + "svint16_t zn", + "svint16_t zm" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "zda": { + "register": "Zreg1.S" + }, + "zm": { + "register": "Zreg3.H" + }, + "zn": { + "register": "Zreg2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdot[_s64]", + "arguments": [ + "svint64_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDOT" + ], + [ + "MOVPRFX", + "SDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdot[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDOT" + ], + [ + "MOVPRFX", + "UDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svdot[_u32_u16]", + "arguments": [ + "svuint32_t zda", + "svuint16_t zn", + "svuint16_t zm" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "zda": { + "register": "Zreg1.S" + }, + "zm": { + "register": "Zreg3.H" + }, + "zn": { + "register": "Zreg2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdot[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDOT" + ], + [ + "MOVPRFX", + "UDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svdot_lane[_f32_f16]", + "arguments": [ + "svfloat32_t zda", + "svfloat16_t zn", + "svfloat16_t zm", + "uint64_t imm_idx" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "imm_idx": { + "immediate": "imm1" + }, + "zda": { + "register": "Zreg1.S" + }, + "zm": { + "register": "Zreg3.H" + }, + "zn": { + "register": "Zreg2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdot_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint8_t op2", + "svint8_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDOT" + ], + [ + "MOVPRFX", + "SDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svdot_lane[_s32_s16]", + "arguments": [ + "svint32_t zda", + "svint16_t zn", + "svint16_t zm", + "uint64_t imm_idx" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_idx": { + "immediate": "imm1" + }, + "zda": { + "register": "Zreg1.S" + }, + "zm": { + "register": "Zreg3.H" + }, + "zn": { + "register": "Zreg2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdot_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SDOT" + ], + [ + "MOVPRFX", + "SDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdot_lane[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint8_t op2", + "svuint8_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDOT" + ], + [ + "MOVPRFX", + "UDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svdot_lane[_u32_u16]", + "arguments": [ + "svuint32_t zda", + "svuint16_t zn", + "svuint16_t zm", + "uint64_t imm_idx" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm_idx": { + "immediate": "imm1" + }, + "zda": { + "register": "Zreg1.S" + }, + "zm": { + "register": "Zreg3.H" + }, + "zn": { + "register": "Zreg2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdot_lane[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint16_t op2", + "svuint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UDOT" + ], + [ + "MOVPRFX", + "UDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_b16", + "arguments": [ + "bool op" + ], + "return_type": { + "value": "svbool_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_b32", + "arguments": [ + "bool op" + ], + "return_type": { + "value": "svbool_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_b64", + "arguments": [ + "bool op" + ], + "return_type": { + "value": "svbool_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_b8", + "arguments": [ + "bool op" + ], + "return_type": { + "value": "svbool_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_f16", + "arguments": [ + "float16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Hop|Wop" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "FDUP" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_f16_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "float16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Ztied.H" + }, + "op": { + "register": "Hop|Wop" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "FCPY" + ], + [ + "CPY" + ], + [ + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_f16_x", + "arguments": [ + "svbool_t pg", + "float16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Hop|Wop" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP" + ], + [ + "FCPY" + ], + [ + "FDUP" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_f16_z", + "arguments": [ + "svbool_t pg", + "float16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Hop|Wop" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP", + "FCPY" + ], + [ + "DUP", + "CPY" + ], + [ + "MOVPRFX", + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_f32", + "arguments": [ + "float32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Sop|Wop" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "FDUP" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_f32_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "float32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Ztied.S" + }, + "op": { + "register": "Sop|Wop" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "FCPY" + ], + [ + "CPY" + ], + [ + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_f32_x", + "arguments": [ + "svbool_t pg", + "float32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Sop|Wop" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP" + ], + [ + "FCPY" + ], + [ + "FDUP" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_f32_z", + "arguments": [ + "svbool_t pg", + "float32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Sop|Wop" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP", + "FCPY" + ], + [ + "DUP", + "CPY" + ], + [ + "MOVPRFX", + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_f64", + "arguments": [ + "float64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Dop|Xop" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "FDUP" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_f64_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "float64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Ztied.D" + }, + "op": { + "register": "Dop|Xop" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "FCPY" + ], + [ + "CPY" + ], + [ + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_f64_x", + "arguments": [ + "svbool_t pg", + "float64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Dop|Xop" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP" + ], + [ + "FCPY" + ], + [ + "FDUP" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_f64_z", + "arguments": [ + "svbool_t pg", + "float64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Dop|Xop" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP", + "FCPY" + ], + [ + "DUP", + "CPY" + ], + [ + "MOVPRFX", + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_s16", + "arguments": [ + "int16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Hop|Wop" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "FDUP" + ], + [ + "DUPM" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_s16_m", + "arguments": [ + "svint16_t inactive", + "svbool_t pg", + "int16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Ztied.H" + }, + "op": { + "register": "Hop|Wop" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "FCPY" + ], + [ + "CPY" + ], + [ + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_s16_x", + "arguments": [ + "svbool_t pg", + "int16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Hop|Wop" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP" + ], + [ + "FCPY" + ], + [ + "FDUP" + ], + [ + "DUPM" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_s16_z", + "arguments": [ + "svbool_t pg", + "int16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Hop|Wop" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP", + "FCPY" + ], + [ + "DUP", + "CPY" + ], + [ + "MOVPRFX", + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_s32", + "arguments": [ + "int32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Sop|Wop" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "FDUP" + ], + [ + "DUPM" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_s32_m", + "arguments": [ + "svint32_t inactive", + "svbool_t pg", + "int32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Ztied.S" + }, + "op": { + "register": "Sop|Wop" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "FCPY" + ], + [ + "CPY" + ], + [ + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_s32_x", + "arguments": [ + "svbool_t pg", + "int32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Sop|Wop" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP" + ], + [ + "FCPY" + ], + [ + "FDUP" + ], + [ + "DUPM" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_s32_z", + "arguments": [ + "svbool_t pg", + "int32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Sop|Wop" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP", + "FCPY" + ], + [ + "DUP", + "CPY" + ], + [ + "MOVPRFX", + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_s64", + "arguments": [ + "int64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Dop|Xop" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "FDUP" + ], + [ + "DUPM" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_s64_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "int64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Ztied.D" + }, + "op": { + "register": "Dop|Xop" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "FCPY" + ], + [ + "CPY" + ], + [ + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_s64_x", + "arguments": [ + "svbool_t pg", + "int64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Dop|Xop" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP" + ], + [ + "FCPY" + ], + [ + "FDUP" + ], + [ + "DUPM" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_s64_z", + "arguments": [ + "svbool_t pg", + "int64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Dop|Xop" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP", + "FCPY" + ], + [ + "DUP", + "CPY" + ], + [ + "MOVPRFX", + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_s8", + "arguments": [ + "int8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Bop|Wop" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "FDUP" + ], + [ + "DUPM" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_s8_m", + "arguments": [ + "svint8_t inactive", + "svbool_t pg", + "int8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Ztied.B" + }, + "op": { + "register": "Bop|Wop" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "FCPY" + ], + [ + "CPY" + ], + [ + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_s8_x", + "arguments": [ + "svbool_t pg", + "int8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Bop|Wop" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP" + ], + [ + "FCPY" + ], + [ + "FDUP" + ], + [ + "DUPM" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_s8_z", + "arguments": [ + "svbool_t pg", + "int8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Bop|Wop" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP", + "FCPY" + ], + [ + "DUP", + "CPY" + ], + [ + "MOVPRFX", + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_u16", + "arguments": [ + "uint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Hop|Wop" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "FDUP" + ], + [ + "DUPM" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_u16_m", + "arguments": [ + "svuint16_t inactive", + "svbool_t pg", + "uint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Ztied.H" + }, + "op": { + "register": "Hop|Wop" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "FCPY" + ], + [ + "CPY" + ], + [ + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_u16_x", + "arguments": [ + "svbool_t pg", + "uint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Hop|Wop" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP" + ], + [ + "FCPY" + ], + [ + "FDUP" + ], + [ + "DUPM" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_u16_z", + "arguments": [ + "svbool_t pg", + "uint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Hop|Wop" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP", + "FCPY" + ], + [ + "DUP", + "CPY" + ], + [ + "MOVPRFX", + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_u32", + "arguments": [ + "uint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Sop|Wop" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "FDUP" + ], + [ + "DUPM" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_u32_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "uint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Ztied.S" + }, + "op": { + "register": "Sop|Wop" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "FCPY" + ], + [ + "CPY" + ], + [ + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_u32_x", + "arguments": [ + "svbool_t pg", + "uint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Sop|Wop" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP" + ], + [ + "FCPY" + ], + [ + "FDUP" + ], + [ + "DUPM" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_u32_z", + "arguments": [ + "svbool_t pg", + "uint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Sop|Wop" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP", + "FCPY" + ], + [ + "DUP", + "CPY" + ], + [ + "MOVPRFX", + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_u64", + "arguments": [ + "uint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Dop|Xop" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "FDUP" + ], + [ + "DUPM" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_u64_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "uint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Ztied.D" + }, + "op": { + "register": "Dop|Xop" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "FCPY" + ], + [ + "CPY" + ], + [ + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_u64_x", + "arguments": [ + "svbool_t pg", + "uint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Dop|Xop" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP" + ], + [ + "FCPY" + ], + [ + "FDUP" + ], + [ + "DUPM" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_u64_z", + "arguments": [ + "svbool_t pg", + "uint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Dop|Xop" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP", + "FCPY" + ], + [ + "DUP", + "CPY" + ], + [ + "MOVPRFX", + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_u8", + "arguments": [ + "uint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Bop|Wop" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "FDUP" + ], + [ + "DUPM" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_u8_m", + "arguments": [ + "svuint8_t inactive", + "svbool_t pg", + "uint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Ztied.B" + }, + "op": { + "register": "Bop|Wop" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "FCPY" + ], + [ + "CPY" + ], + [ + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_u8_x", + "arguments": [ + "svbool_t pg", + "uint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Bop|Wop" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP" + ], + [ + "FCPY" + ], + [ + "FDUP" + ], + [ + "DUPM" + ], + [ + "DUP" + ], + [ + "DUP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup[_n]_u8_z", + "arguments": [ + "svbool_t pg", + "uint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Bop|Wop" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CPY" + ], + [ + "DUP", + "FCPY" + ], + [ + "DUP", + "CPY" + ], + [ + "MOVPRFX", + "CPY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup_lane[_f16]", + "arguments": [ + "svfloat16_t data", + "uint16_t index" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "index": { + "register": "Zindex.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup_lane[_f32]", + "arguments": [ + "svfloat32_t data", + "uint32_t index" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "index": { + "register": "Zindex.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup_lane[_f64]", + "arguments": [ + "svfloat64_t data", + "uint64_t index" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "index": { + "register": "Zindex.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup_lane[_s16]", + "arguments": [ + "svint16_t data", + "uint16_t index" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "index": { + "register": "Zindex.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup_lane[_s32]", + "arguments": [ + "svint32_t data", + "uint32_t index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "index": { + "register": "Zindex.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup_lane[_s64]", + "arguments": [ + "svint64_t data", + "uint64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "index": { + "register": "Zindex.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup_lane[_s8]", + "arguments": [ + "svint8_t data", + "uint8_t index" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.B" + }, + "index": { + "register": "Zindex.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup_lane[_u16]", + "arguments": [ + "svuint16_t data", + "uint16_t index" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "index": { + "register": "Zindex.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup_lane[_u32]", + "arguments": [ + "svuint32_t data", + "uint32_t index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "index": { + "register": "Zindex.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup_lane[_u64]", + "arguments": [ + "svuint64_t data", + "uint64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "index": { + "register": "Zindex.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdup_lane[_u8]", + "arguments": [ + "svuint8_t data", + "uint8_t index" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.B" + }, + "index": { + "register": "Zindex.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq[_n]_b16", + "arguments": [ + "bool x0", + "bool x1", + "bool x2", + "bool x3", + "bool x4", + "bool x5", + "bool x6", + "bool x7" + ], + "return_type": { + "value": "svbool_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq[_n]_b32", + "arguments": [ + "bool x0", + "bool x1", + "bool x2", + "bool x3" + ], + "return_type": { + "value": "svbool_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq[_n]_b64", + "arguments": [ + "bool x0", + "bool x1" + ], + "return_type": { + "value": "svbool_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq[_n]_b8", + "arguments": [ + "bool x0", + "bool x1", + "bool x2", + "bool x3", + "bool x4", + "bool x5", + "bool x6", + "bool x7", + "bool x8", + "bool x9", + "bool x10", + "bool x11", + "bool x12", + "bool x13", + "bool x14", + "bool x15" + ], + "return_type": { + "value": "svbool_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq[_n]_f16", + "arguments": [ + "float16_t x0", + "float16_t x1", + "float16_t x2", + "float16_t x3", + "float16_t x4", + "float16_t x5", + "float16_t x6", + "float16_t x7" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq[_n]_f32", + "arguments": [ + "float32_t x0", + "float32_t x1", + "float32_t x2", + "float32_t x3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq[_n]_f64", + "arguments": [ + "float64_t x0", + "float64_t x1" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq[_n]_s16", + "arguments": [ + "int16_t x0", + "int16_t x1", + "int16_t x2", + "int16_t x3", + "int16_t x4", + "int16_t x5", + "int16_t x6", + "int16_t x7" + ], + "return_type": { + "value": "svint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq[_n]_s32", + "arguments": [ + "int32_t x0", + "int32_t x1", + "int32_t x2", + "int32_t x3" + ], + "return_type": { + "value": "svint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq[_n]_s64", + "arguments": [ + "int64_t x0", + "int64_t x1" + ], + "return_type": { + "value": "svint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq[_n]_s8", + "arguments": [ + "int8_t x0", + "int8_t x1", + "int8_t x2", + "int8_t x3", + "int8_t x4", + "int8_t x5", + "int8_t x6", + "int8_t x7", + "int8_t x8", + "int8_t x9", + "int8_t x10", + "int8_t x11", + "int8_t x12", + "int8_t x13", + "int8_t x14", + "int8_t x15" + ], + "return_type": { + "value": "svint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq[_n]_u16", + "arguments": [ + "uint16_t x0", + "uint16_t x1", + "uint16_t x2", + "uint16_t x3", + "uint16_t x4", + "uint16_t x5", + "uint16_t x6", + "uint16_t x7" + ], + "return_type": { + "value": "svuint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq[_n]_u32", + "arguments": [ + "uint32_t x0", + "uint32_t x1", + "uint32_t x2", + "uint32_t x3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq[_n]_u64", + "arguments": [ + "uint64_t x0", + "uint64_t x1" + ], + "return_type": { + "value": "svuint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq[_n]_u8", + "arguments": [ + "uint8_t x0", + "uint8_t x1", + "uint8_t x2", + "uint8_t x3", + "uint8_t x4", + "uint8_t x5", + "uint8_t x6", + "uint8_t x7", + "uint8_t x8", + "uint8_t x9", + "uint8_t x10", + "uint8_t x11", + "uint8_t x12", + "uint8_t x13", + "uint8_t x14", + "uint8_t x15" + ], + "return_type": { + "value": "svuint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq_lane[_f16]", + "arguments": [ + "svfloat16_t data", + "uint64_t index" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D|Zdata.Q" + }, + "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": { + "register": "Zindices_d.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq_lane[_f32]", + "arguments": [ + "svfloat32_t data", + "uint64_t index" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D|Zdata.Q" + }, + "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": { + "register": "Zindices_d.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq_lane[_f64]", + "arguments": [ + "svfloat64_t data", + "uint64_t index" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D|Zdata.Q" + }, + "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": { + "register": "Zindices_d.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq_lane[_s16]", + "arguments": [ + "svint16_t data", + "uint64_t index" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D|Zdata.Q" + }, + "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": { + "register": "Zindices_d.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq_lane[_s32]", + "arguments": [ + "svint32_t data", + "uint64_t index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D|Zdata.Q" + }, + "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": { + "register": "Zindices_d.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq_lane[_s64]", + "arguments": [ + "svint64_t data", + "uint64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D|Zdata.Q" + }, + "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": { + "register": "Zindices_d.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq_lane[_s8]", + "arguments": [ + "svint8_t data", + "uint64_t index" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D|Zdata.Q" + }, + "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": { + "register": "Zindices_d.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq_lane[_u16]", + "arguments": [ + "svuint16_t data", + "uint64_t index" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D|Zdata.Q" + }, + "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": { + "register": "Zindices_d.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq_lane[_u32]", + "arguments": [ + "svuint32_t data", + "uint64_t index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D|Zdata.Q" + }, + "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": { + "register": "Zindices_d.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq_lane[_u64]", + "arguments": [ + "svuint64_t data", + "uint64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D|Zdata.Q" + }, + "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": { + "register": "Zindices_d.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svdupq_lane[_u8]", + "arguments": [ + "svuint8_t data", + "uint64_t index" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D|Zdata.Q" + }, + "{2 * index, 2 * index + 1, 2 * index, 2 * index + 1, …}": { + "register": "Zindices_d.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ], + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveor3[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "MOVPRFX", + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveor3[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "MOVPRFX", + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveor3[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "MOVPRFX", + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveor3[_n_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B[*]|Ztied3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "MOVPRFX", + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveor3[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "MOVPRFX", + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveor3[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "MOVPRFX", + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveor3[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "MOVPRFX", + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveor3[_n_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B[*]|Ztied3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "MOVPRFX", + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveor3[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "MOVPRFX", + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveor3[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "MOVPRFX", + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveor3[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "MOVPRFX", + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveor3[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B|Ztied3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "MOVPRFX", + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveor3[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "MOVPRFX", + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveor3[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "MOVPRFX", + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveor3[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "MOVPRFX", + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveor3[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B|Ztied3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "EOR3" + ], + [ + "MOVPRFX", + "EOR3" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_b]_z", + "arguments": [ + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ], + [ + "EOR" + ], + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveor[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "EOR" + ], + [ + "MOVPRFX", + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveorbt[_n_s16]", + "arguments": [ + "svint16_t odd", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "odd": { + "register": "Zodd.H|Ztied.H" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORBT" + ], + [ + "MOVPRFX", + "EORBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveorbt[_n_s32]", + "arguments": [ + "svint32_t odd", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "odd": { + "register": "Zodd.S|Ztied.S" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORBT" + ], + [ + "MOVPRFX", + "EORBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveorbt[_n_s64]", + "arguments": [ + "svint64_t odd", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "odd": { + "register": "Zodd.D|Ztied.D" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORBT" + ], + [ + "MOVPRFX", + "EORBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveorbt[_n_s8]", + "arguments": [ + "svint8_t odd", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "odd": { + "register": "Zodd.B|Ztied.B" + }, + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORBT" + ], + [ + "MOVPRFX", + "EORBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveorbt[_n_u16]", + "arguments": [ + "svuint16_t odd", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "odd": { + "register": "Zodd.H|Ztied.H" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORBT" + ], + [ + "MOVPRFX", + "EORBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveorbt[_n_u32]", + "arguments": [ + "svuint32_t odd", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "odd": { + "register": "Zodd.S|Ztied.S" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORBT" + ], + [ + "MOVPRFX", + "EORBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveorbt[_n_u64]", + "arguments": [ + "svuint64_t odd", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "odd": { + "register": "Zodd.D|Ztied.D" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORBT" + ], + [ + "MOVPRFX", + "EORBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveorbt[_n_u8]", + "arguments": [ + "svuint8_t odd", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "odd": { + "register": "Zodd.B|Ztied.B" + }, + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORBT" + ], + [ + "MOVPRFX", + "EORBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveorbt[_s16]", + "arguments": [ + "svint16_t odd", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "odd": { + "register": "Zodd.H|Ztied.H" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORBT" + ], + [ + "MOVPRFX", + "EORBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveorbt[_s32]", + "arguments": [ + "svint32_t odd", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "odd": { + "register": "Zodd.S|Ztied.S" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORBT" + ], + [ + "MOVPRFX", + "EORBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveorbt[_s64]", + "arguments": [ + "svint64_t odd", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "odd": { + "register": "Zodd.D|Ztied.D" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORBT" + ], + [ + "MOVPRFX", + "EORBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveorbt[_s8]", + "arguments": [ + "svint8_t odd", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "odd": { + "register": "Zodd.B|Ztied.B" + }, + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORBT" + ], + [ + "MOVPRFX", + "EORBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveorbt[_u16]", + "arguments": [ + "svuint16_t odd", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "odd": { + "register": "Zodd.H|Ztied.H" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORBT" + ], + [ + "MOVPRFX", + "EORBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveorbt[_u32]", + "arguments": [ + "svuint32_t odd", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "odd": { + "register": "Zodd.S|Ztied.S" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORBT" + ], + [ + "MOVPRFX", + "EORBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveorbt[_u64]", + "arguments": [ + "svuint64_t odd", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "odd": { + "register": "Zodd.D|Ztied.D" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORBT" + ], + [ + "MOVPRFX", + "EORBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveorbt[_u8]", + "arguments": [ + "svuint8_t odd", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "odd": { + "register": "Zodd.B|Ztied.B" + }, + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORBT" + ], + [ + "MOVPRFX", + "EORBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveortb[_n_s16]", + "arguments": [ + "svint16_t even", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Zeven.H|Ztied.H" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORTB" + ], + [ + "MOVPRFX", + "EORTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveortb[_n_s32]", + "arguments": [ + "svint32_t even", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Zeven.S|Ztied.S" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORTB" + ], + [ + "MOVPRFX", + "EORTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveortb[_n_s64]", + "arguments": [ + "svint64_t even", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Zeven.D|Ztied.D" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORTB" + ], + [ + "MOVPRFX", + "EORTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveortb[_n_s8]", + "arguments": [ + "svint8_t even", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Zeven.B|Ztied.B" + }, + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORTB" + ], + [ + "MOVPRFX", + "EORTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveortb[_n_u16]", + "arguments": [ + "svuint16_t even", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Zeven.H|Ztied.H" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORTB" + ], + [ + "MOVPRFX", + "EORTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveortb[_n_u32]", + "arguments": [ + "svuint32_t even", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Zeven.S|Ztied.S" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORTB" + ], + [ + "MOVPRFX", + "EORTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveortb[_n_u64]", + "arguments": [ + "svuint64_t even", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Zeven.D|Ztied.D" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORTB" + ], + [ + "MOVPRFX", + "EORTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveortb[_n_u8]", + "arguments": [ + "svuint8_t even", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Zeven.B|Ztied.B" + }, + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORTB" + ], + [ + "MOVPRFX", + "EORTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveortb[_s16]", + "arguments": [ + "svint16_t even", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Zeven.H|Ztied.H" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORTB" + ], + [ + "MOVPRFX", + "EORTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveortb[_s32]", + "arguments": [ + "svint32_t even", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Zeven.S|Ztied.S" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORTB" + ], + [ + "MOVPRFX", + "EORTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveortb[_s64]", + "arguments": [ + "svint64_t even", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Zeven.D|Ztied.D" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORTB" + ], + [ + "MOVPRFX", + "EORTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveortb[_s8]", + "arguments": [ + "svint8_t even", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Zeven.B|Ztied.B" + }, + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORTB" + ], + [ + "MOVPRFX", + "EORTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveortb[_u16]", + "arguments": [ + "svuint16_t even", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Zeven.H|Ztied.H" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORTB" + ], + [ + "MOVPRFX", + "EORTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveortb[_u32]", + "arguments": [ + "svuint32_t even", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Zeven.S|Ztied.S" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORTB" + ], + [ + "MOVPRFX", + "EORTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveortb[_u64]", + "arguments": [ + "svuint64_t even", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Zeven.D|Ztied.D" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORTB" + ], + [ + "MOVPRFX", + "EORTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "sveortb[_u8]", + "arguments": [ + "svuint8_t even", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Zeven.B|Ztied.B" + }, + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORTB" + ], + [ + "MOVPRFX", + "EORTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveorv[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveorv[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveorv[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveorv[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "int8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveorv[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveorv[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveorv[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "sveorv[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "uint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EORV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svexpa[_f16]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FEXPA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svexpa[_f32]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FEXPA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svexpa[_f64]", + "arguments": [ + "svuint64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FEXPA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svext[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 127 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EXT" + ], + [ + "MOVPRFX", + "EXT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svext[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 63 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EXT" + ], + [ + "MOVPRFX", + "EXT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svext[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 31 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EXT" + ], + [ + "MOVPRFX", + "EXT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svext[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 127 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EXT" + ], + [ + "MOVPRFX", + "EXT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svext[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 63 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EXT" + ], + [ + "MOVPRFX", + "EXT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svext[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 31 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EXT" + ], + [ + "MOVPRFX", + "EXT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svext[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 255 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EXT" + ], + [ + "MOVPRFX", + "EXT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svext[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 127 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EXT" + ], + [ + "MOVPRFX", + "EXT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svext[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 63 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EXT" + ], + [ + "MOVPRFX", + "EXT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svext[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 31 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EXT" + ], + [ + "MOVPRFX", + "EXT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svext[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 255 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EXT" + ], + [ + "MOVPRFX", + "EXT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_s16]_m", + "arguments": [ + "svint16_t inactive", + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SXTB" + ], + [ + "MOVPRFX", + "SXTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SXTB" + ], + [ + "MOVPRFX", + "SXTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SXTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_s32]_m", + "arguments": [ + "svint32_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SXTB" + ], + [ + "MOVPRFX", + "SXTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SXTB" + ], + [ + "MOVPRFX", + "SXTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SXTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_s64]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SXTB" + ], + [ + "MOVPRFX", + "SXTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SXTB" + ], + [ + "MOVPRFX", + "SXTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SXTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_u16]_m", + "arguments": [ + "svuint16_t inactive", + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTB" + ], + [ + "MOVPRFX", + "UXTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTB" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UXTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_u32]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTB" + ], + [ + "MOVPRFX", + "UXTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTB" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UXTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_u64]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTB" + ], + [ + "MOVPRFX", + "UXTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTB" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextb[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UXTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svexth[_s32]_m", + "arguments": [ + "svint32_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SXTH" + ], + [ + "MOVPRFX", + "SXTH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svexth[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SXTH" + ], + [ + "MOVPRFX", + "SXTH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svexth[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SXTH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svexth[_s64]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SXTH" + ], + [ + "MOVPRFX", + "SXTH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svexth[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SXTH" + ], + [ + "MOVPRFX", + "SXTH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svexth[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SXTH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svexth[_u32]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTH" + ], + [ + "MOVPRFX", + "UXTH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svexth[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTH" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svexth[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UXTH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svexth[_u64]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTH" + ], + [ + "MOVPRFX", + "UXTH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svexth[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTH" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svexth[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UXTH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextw[_s64]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SXTW" + ], + [ + "MOVPRFX", + "SXTW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextw[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SXTW" + ], + [ + "MOVPRFX", + "SXTW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextw[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SXTW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextw[_u64]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTW" + ], + [ + "MOVPRFX", + "UXTW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextw[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UXTW" + ], + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svextw[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UXTW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svget2[_b]", + "arguments": [ + "svboolx2_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svbool_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget2[_f16]", + "arguments": [ + "svfloat16x2_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget2[_f32]", + "arguments": [ + "svfloat32x2_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget2[_f64]", + "arguments": [ + "svfloat64x2_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget2[_s16]", + "arguments": [ + "svint16x2_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget2[_s32]", + "arguments": [ + "svint32x2_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget2[_s64]", + "arguments": [ + "svint64x2_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget2[_s8]", + "arguments": [ + "svint8x2_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget2[_u16]", + "arguments": [ + "svuint16x2_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget2[_u32]", + "arguments": [ + "svuint32x2_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget2[_u64]", + "arguments": [ + "svuint64x2_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget2[_u8]", + "arguments": [ + "svuint8x2_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget3[_f16]", + "arguments": [ + "svfloat16x3_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget3[_f32]", + "arguments": [ + "svfloat32x3_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget3[_f64]", + "arguments": [ + "svfloat64x3_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget3[_s16]", + "arguments": [ + "svint16x3_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget3[_s32]", + "arguments": [ + "svint32x3_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget3[_s64]", + "arguments": [ + "svint64x3_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget3[_s8]", + "arguments": [ + "svint8x3_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget3[_u16]", + "arguments": [ + "svuint16x3_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget3[_u32]", + "arguments": [ + "svuint32x3_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget3[_u64]", + "arguments": [ + "svuint64x3_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget3[_u8]", + "arguments": [ + "svuint8x3_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svget4[_b]", + "arguments": [ + "svboolx4_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svbool_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget4[_f16]", + "arguments": [ + "svfloat16x4_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget4[_f32]", + "arguments": [ + "svfloat32x4_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget4[_f64]", + "arguments": [ + "svfloat64x4_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget4[_s16]", + "arguments": [ + "svint16x4_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget4[_s32]", + "arguments": [ + "svint32x4_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget4[_s64]", + "arguments": [ + "svint64x4_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget4[_s8]", + "arguments": [ + "svint8x4_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget4[_u16]", + "arguments": [ + "svuint16x4_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget4[_u32]", + "arguments": [ + "svuint32x4_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget4[_u64]", + "arguments": [ + "svuint64x4_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svget4[_u8]", + "arguments": [ + "svuint8x4_t tuple", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHADD" + ], + [ + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHADD" + ], + [ + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHADD" + ], + [ + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHADD" + ], + [ + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHADD" + ], + [ + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHADD" + ], + [ + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHADD" + ], + [ + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHADD" + ], + [ + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHADD" + ], + [ + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHADD" + ], + [ + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHADD" + ], + [ + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHADD" + ], + [ + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHADD" + ], + [ + "MOVPRFX", + "SHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHADD" + ], + [ + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHADD" + ], + [ + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHADD" + ], + [ + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHADD" + ], + [ + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhadd[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHADD" + ], + [ + "MOVPRFX", + "UHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhistcnt[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "HISTCNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhistcnt[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "HISTCNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhistcnt[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "HISTCNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhistcnt[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "HISTCNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhistseg[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "HISTSEG" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhistseg[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "HISTSEG" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUB" + ], + [ + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUB" + ], + [ + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUB" + ], + [ + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUB" + ], + [ + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUB" + ], + [ + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUB" + ], + [ + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUB" + ], + [ + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUB" + ], + [ + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUB" + ], + [ + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUB" + ], + [ + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUB" + ], + [ + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUB" + ], + [ + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUB" + ], + [ + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUB" + ], + [ + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUB" + ], + [ + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUB" + ], + [ + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsub[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUBR" + ], + [ + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUBR" + ], + [ + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUBR" + ], + [ + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUBR" + ], + [ + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUBR" + ], + [ + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUBR" + ], + [ + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUBR" + ], + [ + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUBR" + ], + [ + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUBR" + ], + [ + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUBR" + ], + [ + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUBR" + ], + [ + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHSUBR" + ], + [ + "SHSUB" + ], + [ + "MOVPRFX", + "SHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SHSUBR" + ], + [ + "MOVPRFX", + "SHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUBR" + ], + [ + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUBR" + ], + [ + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUBR" + ], + [ + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UHSUBR" + ], + [ + "UHSUB" + ], + [ + "MOVPRFX", + "UHSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svhsubr[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UHSUBR" + ], + [ + "MOVPRFX", + "UHSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svindex_s16", + "arguments": [ + "int16_t base", + "int16_t step" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Wbase" + }, + "step": { + "register": "Wstep" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INDEX" + ], + [ + "INDEX" + ], + [ + "INDEX" + ], + [ + "INDEX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svindex_s32", + "arguments": [ + "int32_t base", + "int32_t step" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Wbase" + }, + "step": { + "register": "Wstep" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INDEX" + ], + [ + "INDEX" + ], + [ + "INDEX" + ], + [ + "INDEX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svindex_s64", + "arguments": [ + "int64_t base", + "int64_t step" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "step": { + "register": "Xstep" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INDEX" + ], + [ + "INDEX" + ], + [ + "INDEX" + ], + [ + "INDEX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svindex_s8", + "arguments": [ + "int8_t base", + "int8_t step" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Wbase" + }, + "step": { + "register": "Wstep" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INDEX" + ], + [ + "INDEX" + ], + [ + "INDEX" + ], + [ + "INDEX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svindex_u16", + "arguments": [ + "uint16_t base", + "uint16_t step" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Wbase" + }, + "step": { + "register": "Wstep" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INDEX" + ], + [ + "INDEX" + ], + [ + "INDEX" + ], + [ + "INDEX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svindex_u32", + "arguments": [ + "uint32_t base", + "uint32_t step" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Wbase" + }, + "step": { + "register": "Wstep" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INDEX" + ], + [ + "INDEX" + ], + [ + "INDEX" + ], + [ + "INDEX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svindex_u64", + "arguments": [ + "uint64_t base", + "uint64_t step" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "step": { + "register": "Xstep" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INDEX" + ], + [ + "INDEX" + ], + [ + "INDEX" + ], + [ + "INDEX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svindex_u8", + "arguments": [ + "uint8_t base", + "uint8_t step" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Wbase" + }, + "step": { + "register": "Wstep" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INDEX" + ], + [ + "INDEX" + ], + [ + "INDEX" + ], + [ + "INDEX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svinsr[_n_f16]", + "arguments": [ + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Hop2|Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INSR" + ], + [ + "INSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svinsr[_n_f32]", + "arguments": [ + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Sop2|Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INSR" + ], + [ + "INSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svinsr[_n_f64]", + "arguments": [ + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Dop2|Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INSR" + ], + [ + "INSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svinsr[_n_s16]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Hop2|Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INSR" + ], + [ + "INSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svinsr[_n_s32]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Sop2|Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INSR" + ], + [ + "INSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svinsr[_n_s64]", + "arguments": [ + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Dop2|Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INSR" + ], + [ + "INSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svinsr[_n_s8]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Bop2|Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INSR" + ], + [ + "INSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svinsr[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Hop2|Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INSR" + ], + [ + "INSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svinsr[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Sop2|Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INSR" + ], + [ + "INSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svinsr[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Dop2|Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INSR" + ], + [ + "INSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svinsr[_n_u8]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Bop2|Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "INSR" + ], + [ + "INSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlasta[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTA" + ], + [ + "LASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlasta[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "float32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTA" + ], + [ + "LASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlasta[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "float64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTA" + ], + [ + "LASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlasta[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTA" + ], + [ + "LASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlasta[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTA" + ], + [ + "LASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlasta[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTA" + ], + [ + "LASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlasta[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "int8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTA" + ], + [ + "LASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlasta[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTA" + ], + [ + "LASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlasta[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTA" + ], + [ + "LASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlasta[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTA" + ], + [ + "LASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlasta[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "uint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTA" + ], + [ + "LASTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlastb[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTB" + ], + [ + "LASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlastb[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "float32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTB" + ], + [ + "LASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlastb[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "float64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTB" + ], + [ + "LASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlastb[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTB" + ], + [ + "LASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlastb[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTB" + ], + [ + "LASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlastb[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTB" + ], + [ + "LASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlastb[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "int8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTB" + ], + [ + "LASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlastb[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTB" + ], + [ + "LASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlastb[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTB" + ], + [ + "LASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlastb[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTB" + ], + [ + "LASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlastb[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "uint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LASTB" + ], + [ + "LASTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1[_f16]", + "arguments": [ + "svbool_t pg", + "const float16_t *base" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_f16]_x2", + "arguments": [ + "svcount_t png", + "float16_t const * rn" + ], + "return_type": { + "value": "svfloat16x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_f16]_x4", + "arguments": [ + "svcount_t png", + "float16_t const * rn" + ], + "return_type": { + "value": "svfloat16x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_f32]_x2", + "arguments": [ + "svcount_t png", + "float32_t const * rn" + ], + "return_type": { + "value": "svfloat32x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_f32]_x4", + "arguments": [ + "svcount_t png", + "float32_t const * rn" + ], + "return_type": { + "value": "svfloat32x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ], + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_f64]_x2", + "arguments": [ + "svcount_t png", + "float64_t const * rn" + ], + "return_type": { + "value": "svfloat64x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_f64]_x4", + "arguments": [ + "svcount_t png", + "float64_t const * rn" + ], + "return_type": { + "value": "svfloat64x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1[_s16]", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_s16]_x2", + "arguments": [ + "svcount_t png", + "int16_t const * rn" + ], + "return_type": { + "value": "svint16x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_s16]_x4", + "arguments": [ + "svcount_t png", + "int16_t const * rn" + ], + "return_type": { + "value": "svint16x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_s32]_x2", + "arguments": [ + "svcount_t png", + "int32_t const * rn" + ], + "return_type": { + "value": "svint32x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_s32]_x4", + "arguments": [ + "svcount_t png", + "int32_t const * rn" + ], + "return_type": { + "value": "svint32x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ], + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_s64]_x2", + "arguments": [ + "svcount_t png", + "int64_t const * rn" + ], + "return_type": { + "value": "svint64x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_s64]_x4", + "arguments": [ + "svcount_t png", + "int64_t const * rn" + ], + "return_type": { + "value": "svint64x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1[_s8]", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_s8]_x2", + "arguments": [ + "svcount_t png", + "int8_t const * rn" + ], + "return_type": { + "value": "svint8x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_s8]_x4", + "arguments": [ + "svcount_t png", + "int8_t const * rn" + ], + "return_type": { + "value": "svint8x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1[_u16]", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_u16]_x2", + "arguments": [ + "svcount_t png", + "uint16_t const * rn" + ], + "return_type": { + "value": "svuint16x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_u16]_x4", + "arguments": [ + "svcount_t png", + "uint16_t const * rn" + ], + "return_type": { + "value": "svuint16x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_u32]_x2", + "arguments": [ + "svcount_t png", + "uint32_t const * rn" + ], + "return_type": { + "value": "svuint32x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_u32]_x4", + "arguments": [ + "svcount_t png", + "uint32_t const * rn" + ], + "return_type": { + "value": "svuint32x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ], + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_u64]_x2", + "arguments": [ + "svcount_t png", + "uint64_t const * rn" + ], + "return_type": { + "value": "svuint64x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_u64]_x4", + "arguments": [ + "svcount_t png", + "uint64_t const * rn" + ], + "return_type": { + "value": "svuint64x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1[_u8]", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_u8]_x2", + "arguments": [ + "svcount_t png", + "uint8_t const * rn" + ], + "return_type": { + "value": "svuint8x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1[_u8]_x4", + "arguments": [ + "svcount_t png", + "uint8_t const * rn" + ], + "return_type": { + "value": "svuint8x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u32base]_f32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u32base]_index_f32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u32base]_index_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u32base]_index_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u32base]_offset_f32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u32base]_offset_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u32base]_offset_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u32base]_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u32base]_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u64base]_f64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u64base]_index_f64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ], + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u64base]_index_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ], + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u64base]_index_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ], + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u64base]_offset_f64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ], + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ], + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ], + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[s32]index[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base", + "svint32_t indices" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[s32]index[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svint32_t indices" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[s32]index[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[s32]offset[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[s32]offset[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[s32]offset[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[s64]index[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[s64]index[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[s64]index[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[s64]offset[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[s64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[s64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[u32]index[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base", + "svuint32_t indices" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[u32]index[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint32_t indices" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[u32]index[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[u32]offset[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[u32]offset[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[u32]offset[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[u64]index[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[u64]index[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[u64]index[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[u64]offset[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[u64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_gather_[u64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_vnum[_f16]", + "arguments": [ + "svbool_t pg", + "const float16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_f16]_x2", + "arguments": [ + "svcount_t png", + "float16_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat16x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_f16]_x4", + "arguments": [ + "svcount_t png", + "float16_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat16x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_vnum[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_f32]_x2", + "arguments": [ + "svcount_t png", + "float32_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat32x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_f32]_x4", + "arguments": [ + "svcount_t png", + "float32_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat32x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_vnum[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ], + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_f64]_x2", + "arguments": [ + "svcount_t png", + "float64_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat64x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_f64]_x4", + "arguments": [ + "svcount_t png", + "float64_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat64x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_vnum[_s16]", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_s16]_x2", + "arguments": [ + "svcount_t png", + "int16_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svint16x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_s16]_x4", + "arguments": [ + "svcount_t png", + "int16_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svint16x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_vnum[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_s32]_x2", + "arguments": [ + "svcount_t png", + "int32_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svint32x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_s32]_x4", + "arguments": [ + "svcount_t png", + "int32_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svint32x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_vnum[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ], + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_s64]_x2", + "arguments": [ + "svcount_t png", + "int64_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svint64x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_s64]_x4", + "arguments": [ + "svcount_t png", + "int64_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svint64x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_vnum[_s8]", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_s8]_x2", + "arguments": [ + "svcount_t png", + "int8_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svint8x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MUL", + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_s8]_x4", + "arguments": [ + "svcount_t png", + "int8_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svint8x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MUL", + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_vnum[_u16]", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_u16]_x2", + "arguments": [ + "svcount_t png", + "uint16_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_u16]_x4", + "arguments": [ + "svcount_t png", + "uint16_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_vnum[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_u32]_x2", + "arguments": [ + "svcount_t png", + "uint32_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_u32]_x4", + "arguments": [ + "svcount_t png", + "uint32_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_vnum[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1D" + ], + [ + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_u64]_x2", + "arguments": [ + "svcount_t png", + "uint64_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_u64]_x4", + "arguments": [ + "svcount_t png", + "uint64_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LD1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1_vnum[_u8]", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_u8]_x2", + "arguments": [ + "svcount_t png", + "uint8_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svuint8x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MUL", + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svld1_vnum[_u8]_x4", + "arguments": [ + "svcount_t png", + "uint8_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svuint8x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MUL", + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ro[_f16]", + "arguments": [ + "svbool_t pg", + "const float16_t *base" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1ROH" + ], + [ + "LD1ROH" + ], + [ + "LD1ROH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ro[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1ROW" + ], + [ + "LD1ROW" + ], + [ + "LD1ROW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ro[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1ROD" + ], + [ + "LD1ROD" + ], + [ + "LD1ROD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ro[_s16]", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1ROH" + ], + [ + "LD1ROH" + ], + [ + "LD1ROH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ro[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1ROW" + ], + [ + "LD1ROW" + ], + [ + "LD1ROW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ro[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1ROD" + ], + [ + "LD1ROD" + ], + [ + "LD1ROD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ro[_s8]", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1ROB" + ], + [ + "LD1ROB" + ], + [ + "LD1ROB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ro[_u16]", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1ROH" + ], + [ + "LD1ROH" + ], + [ + "LD1ROH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ro[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1ROW" + ], + [ + "LD1ROW" + ], + [ + "LD1ROW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ro[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1ROD" + ], + [ + "LD1ROD" + ], + [ + "LD1ROD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ro[_u8]", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1ROB" + ], + [ + "LD1ROB" + ], + [ + "LD1ROB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1rq[_f16]", + "arguments": [ + "svbool_t pg", + "const float16_t *base" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1RQH" + ], + [ + "LD1RQH" + ], + [ + "LD1RQH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1rq[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1RQW" + ], + [ + "LD1RQW" + ], + [ + "LD1RQW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1rq[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1RQD" + ], + [ + "LD1RQD" + ], + [ + "LD1RQD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1rq[_s16]", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1RQH" + ], + [ + "LD1RQH" + ], + [ + "LD1RQH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1rq[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1RQW" + ], + [ + "LD1RQW" + ], + [ + "LD1RQW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1rq[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1RQD" + ], + [ + "LD1RQD" + ], + [ + "LD1RQD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1rq[_s8]", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1RQB" + ], + [ + "LD1RQB" + ], + [ + "LD1RQB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1rq[_u16]", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1RQH" + ], + [ + "LD1RQH" + ], + [ + "LD1RQH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1rq[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1RQW" + ], + [ + "LD1RQW" + ], + [ + "LD1RQW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1rq[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1RQD" + ], + [ + "LD1RQD" + ], + [ + "LD1RQD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1rq[_u8]", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1RQB" + ], + [ + "LD1RQB" + ], + [ + "LD1RQB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_gather[_u32base]_offset_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ], + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_gather[_u32base]_offset_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ], + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_gather[_u32base]_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_gather[_u32base]_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ], + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ], + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_gather_[s32]offset_s32", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_gather_[s32]offset_u32", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_gather_[u32]offset_s32", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_gather_[u32]offset_u32", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_s16", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ], + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_s32", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ], + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_s64", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ], + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_u16", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ], + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_u32", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ], + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_u64", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ], + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_vnum_s16", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ], + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_vnum_s32", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ], + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_vnum_s64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ], + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_vnum_u16", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ], + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_vnum_u32", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ], + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sb_vnum_u64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SB" + ], + [ + "LD1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather[_u32base]_index_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ], + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather[_u32base]_index_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ], + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather[_u32base]_offset_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ], + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather[_u32base]_offset_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ], + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather[_u32base]_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather[_u32base]_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather[_u64base]_index_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ], + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather[_u64base]_index_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ], + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ], + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ], + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather_[s32]index_s32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint32_t indices" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather_[s32]index_u32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather_[s32]offset_s32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather_[s32]offset_u32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather_[s64]index_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather_[s64]index_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather_[u32]index_s32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint32_t indices" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather_[u32]index_u32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather_[u32]offset_s32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather_[u32]offset_u32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather_[u64]index_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather_[u64]index_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_s32", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ], + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ], + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_u32", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ], + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ], + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_vnum_s32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ], + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_vnum_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ], + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_vnum_u32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ], + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sh_vnum_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SH" + ], + [ + "LD1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_gather[_u64base]_index_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ], + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_gather[_u64base]_index_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ], + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ], + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ], + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_gather_[s64]index_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_gather_[s64]index_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_gather_[u64]index_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_gather_[u64]index_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ], + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ], + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_vnum_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ], + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1sw_vnum_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1SW" + ], + [ + "LD1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_gather[_u32base]_offset_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_gather[_u32base]_offset_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_gather[_u32base]_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_gather[_u32base]_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_gather_[s32]offset_s32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_gather_[s32]offset_u32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_gather_[u32]offset_s32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_gather_[u32]offset_u32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_s16", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_s32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_s64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_u16", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_u32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_u64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_vnum_s16", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_vnum_s32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_vnum_s64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_vnum_u16", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_vnum_u32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1ub_vnum_u64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1B" + ], + [ + "LD1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather[_u32base]_index_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather[_u32base]_index_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather[_u32base]_offset_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather[_u32base]_offset_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather[_u32base]_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather[_u32base]_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather[_u64base]_index_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather[_u64base]_index_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather_[s32]index_s32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint32_t indices" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather_[s32]index_u32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather_[s32]offset_s32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather_[s32]offset_u32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather_[s64]index_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather_[s64]index_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather_[u32]index_s32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint32_t indices" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather_[u32]index_u32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather_[u32]offset_s32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather_[u32]offset_u32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather_[u64]index_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather_[u64]index_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_s32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_u32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_vnum_s32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_vnum_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_vnum_u32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uh_vnum_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1H" + ], + [ + "LD1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_gather[_u64base]_index_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_gather[_u64base]_index_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_gather_[s64]index_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_gather_[s64]index_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_gather_[u64]index_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_gather_[u64]index_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_vnum_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld1uw_vnum_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD1W" + ], + [ + "LD1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2[_f16]", + "arguments": [ + "svbool_t pg", + "const float16_t *base" + ], + "return_type": { + "value": "svfloat16x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2H" + ], + [ + "LD2H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base" + ], + "return_type": { + "value": "svfloat32x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2W" + ], + [ + "LD2W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base" + ], + "return_type": { + "value": "svfloat64x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2D" + ], + [ + "LD2D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2[_s16]", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svint16x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2H" + ], + [ + "LD2H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base" + ], + "return_type": { + "value": "svint32x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2W" + ], + [ + "LD2W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base" + ], + "return_type": { + "value": "svint64x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2D" + ], + [ + "LD2D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2[_s8]", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint8x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2B" + ], + [ + "LD2B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2[_u16]", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svuint16x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2H" + ], + [ + "LD2H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base" + ], + "return_type": { + "value": "svuint32x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2W" + ], + [ + "LD2W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base" + ], + "return_type": { + "value": "svuint64x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2D" + ], + [ + "LD2D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2[_u8]", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint8x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2B" + ], + [ + "LD2B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2_vnum[_f16]", + "arguments": [ + "svbool_t pg", + "const float16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat16x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2H" + ], + [ + "LD2H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2_vnum[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat32x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2W" + ], + [ + "LD2W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2_vnum[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat64x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2D" + ], + [ + "LD2D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2_vnum[_s16]", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint16x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2H" + ], + [ + "LD2H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2_vnum[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2W" + ], + [ + "LD2W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2_vnum[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2D" + ], + [ + "LD2D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2_vnum[_s8]", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint8x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2B" + ], + [ + "LD2B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2_vnum[_u16]", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2H" + ], + [ + "LD2H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2_vnum[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2W" + ], + [ + "LD2W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2_vnum[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2D" + ], + [ + "LD2D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld2_vnum[_u8]", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint8x2_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD2B" + ], + [ + "LD2B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3[_f16]", + "arguments": [ + "svbool_t pg", + "const float16_t *base" + ], + "return_type": { + "value": "svfloat16x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3H" + ], + [ + "LD3H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base" + ], + "return_type": { + "value": "svfloat32x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3W" + ], + [ + "LD3W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base" + ], + "return_type": { + "value": "svfloat64x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3D" + ], + [ + "LD3D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3[_s16]", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svint16x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3H" + ], + [ + "LD3H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base" + ], + "return_type": { + "value": "svint32x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3W" + ], + [ + "LD3W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base" + ], + "return_type": { + "value": "svint64x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3D" + ], + [ + "LD3D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3[_s8]", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint8x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3B" + ], + [ + "LD3B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3[_u16]", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svuint16x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3H" + ], + [ + "LD3H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base" + ], + "return_type": { + "value": "svuint32x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3W" + ], + [ + "LD3W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base" + ], + "return_type": { + "value": "svuint64x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3D" + ], + [ + "LD3D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3[_u8]", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint8x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3B" + ], + [ + "LD3B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3_vnum[_f16]", + "arguments": [ + "svbool_t pg", + "const float16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat16x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3H" + ], + [ + "LD3H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3_vnum[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat32x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3W" + ], + [ + "LD3W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3_vnum[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat64x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3D" + ], + [ + "LD3D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3_vnum[_s16]", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint16x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3H" + ], + [ + "LD3H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3_vnum[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3W" + ], + [ + "LD3W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3_vnum[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3D" + ], + [ + "LD3D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3_vnum[_s8]", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint8x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3B" + ], + [ + "LD3B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3_vnum[_u16]", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3H" + ], + [ + "LD3H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3_vnum[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3W" + ], + [ + "LD3W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3_vnum[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3D" + ], + [ + "LD3D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld3_vnum[_u8]", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint8x3_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD3B" + ], + [ + "LD3B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4[_f16]", + "arguments": [ + "svbool_t pg", + "const float16_t *base" + ], + "return_type": { + "value": "svfloat16x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4H" + ], + [ + "LD4H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base" + ], + "return_type": { + "value": "svfloat32x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4W" + ], + [ + "LD4W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base" + ], + "return_type": { + "value": "svfloat64x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4D" + ], + [ + "LD4D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4[_s16]", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svint16x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4H" + ], + [ + "LD4H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base" + ], + "return_type": { + "value": "svint32x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4W" + ], + [ + "LD4W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base" + ], + "return_type": { + "value": "svint64x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4D" + ], + [ + "LD4D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4[_s8]", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint8x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4B" + ], + [ + "LD4B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4[_u16]", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svuint16x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4H" + ], + [ + "LD4H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base" + ], + "return_type": { + "value": "svuint32x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4W" + ], + [ + "LD4W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base" + ], + "return_type": { + "value": "svuint64x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4D" + ], + [ + "LD4D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4[_u8]", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint8x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4B" + ], + [ + "LD4B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4_vnum[_f16]", + "arguments": [ + "svbool_t pg", + "const float16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat16x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4H" + ], + [ + "LD4H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4_vnum[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat32x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4W" + ], + [ + "LD4W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4_vnum[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat64x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4D" + ], + [ + "LD4D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4_vnum[_s16]", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint16x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4H" + ], + [ + "LD4H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4_vnum[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4W" + ], + [ + "LD4W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4_vnum[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4D" + ], + [ + "LD4D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4_vnum[_s8]", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint8x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4B" + ], + [ + "LD4B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4_vnum[_u16]", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4H" + ], + [ + "LD4H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4_vnum[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4W" + ], + [ + "LD4W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4_vnum[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4D" + ], + [ + "LD4D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svld4_vnum[_u8]", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint8x4_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LD4B" + ], + [ + "LD4B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1[_f16]", + "arguments": [ + "svbool_t pg", + "const float16_t *base" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ], + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ], + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ], + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1[_s16]", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ], + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ], + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ], + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1[_s8]", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ], + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1[_u16]", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ], + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ], + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ], + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1[_u8]", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ], + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u32base]_f32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u32base]_index_f32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ], + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u32base]_index_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ], + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u32base]_index_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ], + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u32base]_offset_f32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ], + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u32base]_offset_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ], + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u32base]_offset_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ], + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u32base]_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u32base]_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u64base]_f64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u64base]_index_f64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ], + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u64base]_index_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ], + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u64base]_index_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ], + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u64base]_offset_f64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ], + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ], + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ], + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[s32]index[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base", + "svint32_t indices" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[s32]index[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svint32_t indices" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[s32]index[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[s32]offset[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[s32]offset[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[s32]offset[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[s64]index[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[s64]index[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[s64]index[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[s64]offset[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[s64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[s64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[u32]index[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base", + "svuint32_t indices" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[u32]index[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint32_t indices" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[u32]index[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[u32]offset[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[u32]offset[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[u32]offset[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[u64]index[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[u64]index[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[u64]index[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[u64]offset[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[u64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_gather_[u64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_vnum[_f16]", + "arguments": [ + "svbool_t pg", + "const float16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_vnum[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_vnum[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_vnum[_s16]", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_vnum[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_vnum[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_vnum[_s8]", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_vnum[_u16]", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_vnum[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_vnum[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1_vnum[_u8]", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_gather[_u32base]_offset_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ], + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_gather[_u32base]_offset_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ], + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_gather[_u32base]_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_gather[_u32base]_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ], + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ], + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_gather_[s32]offset_s32", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_gather_[s32]offset_u32", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_gather_[u32]offset_s32", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_gather_[u32]offset_u32", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_s16", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ], + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_s32", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ], + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_s64", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ], + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_u16", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ], + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_u32", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ], + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_u64", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ], + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_vnum_s16", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_vnum_s32", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_vnum_s64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_vnum_u16", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_vnum_u32", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sb_vnum_u64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather[_u32base]_index_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ], + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather[_u32base]_index_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ], + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather[_u32base]_offset_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ], + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather[_u32base]_offset_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ], + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather[_u32base]_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather[_u32base]_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather[_u64base]_index_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ], + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather[_u64base]_index_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ], + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ], + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ], + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather_[s32]index_s32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint32_t indices" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather_[s32]index_u32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather_[s32]offset_s32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather_[s32]offset_u32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather_[s64]index_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather_[s64]index_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather_[u32]index_s32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint32_t indices" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather_[u32]index_u32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather_[u32]offset_s32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather_[u32]offset_u32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather_[u64]index_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather_[u64]index_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_s32", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ], + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ], + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_u32", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ], + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ], + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_vnum_s32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_vnum_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_vnum_u32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sh_vnum_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_gather[_u64base]_index_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ], + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_gather[_u64base]_index_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ], + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ], + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ], + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_gather_[s64]index_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_gather_[s64]index_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_gather_[u64]index_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_gather_[u64]index_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ], + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ], + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_vnum_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1sw_vnum_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_gather[_u32base]_offset_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ], + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_gather[_u32base]_offset_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ], + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_gather[_u32base]_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_gather[_u32base]_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ], + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ], + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_gather_[s32]offset_s32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_gather_[s32]offset_u32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_gather_[u32]offset_s32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_gather_[u32]offset_u32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_s16", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ], + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_s32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ], + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_s64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ], + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_u16", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ], + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_u32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ], + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_u64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ], + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_vnum_s16", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_vnum_s32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_vnum_s64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_vnum_u16", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_vnum_u32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1ub_vnum_u64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather[_u32base]_index_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ], + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather[_u32base]_index_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ], + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather[_u32base]_offset_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ], + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather[_u32base]_offset_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ], + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather[_u32base]_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather[_u32base]_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather[_u64base]_index_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ], + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather[_u64base]_index_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ], + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ], + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ], + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather_[s32]index_s32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint32_t indices" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather_[s32]index_u32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather_[s32]offset_s32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather_[s32]offset_u32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather_[s64]index_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather_[s64]index_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather_[u32]index_s32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint32_t indices" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather_[u32]index_u32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather_[u32]offset_s32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather_[u32]offset_u32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather_[u64]index_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather_[u64]index_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_s32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ], + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ], + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_u32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ], + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ], + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_vnum_s32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_vnum_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_vnum_u32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uh_vnum_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_gather[_u64base]_index_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ], + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_gather[_u64base]_index_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ], + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ], + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ], + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_gather_[s64]index_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_gather_[s64]index_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_gather_[u64]index_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_gather_[u64]index_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ], + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ], + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_vnum_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldff1uw_vnum_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDFF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1[_f16]", + "arguments": [ + "svbool_t pg", + "const float16_t *base" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1[_s16]", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1[_s8]", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1[_u16]", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1[_u8]", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1_vnum[_f16]", + "arguments": [ + "svbool_t pg", + "const float16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcnth() * 2": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1H" + ], + [ + "LDNF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1_vnum[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntw() * 4": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1W" + ], + [ + "LDNF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1_vnum[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntd() * 8": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1D" + ], + [ + "LDNF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1_vnum[_s16]", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcnth() * 2": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1H" + ], + [ + "LDNF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1_vnum[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntw() * 4": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1W" + ], + [ + "LDNF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1_vnum[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntd() * 8": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1D" + ], + [ + "LDNF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1_vnum[_s8]", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntb()": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1B" + ], + [ + "LDNF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1_vnum[_u16]", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcnth() * 2": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1H" + ], + [ + "LDNF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1_vnum[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntw() * 4": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1W" + ], + [ + "LDNF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1_vnum[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntd() * 8": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1D" + ], + [ + "LDNF1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1_vnum[_u8]", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntb()": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1B" + ], + [ + "LDNF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sb_s16", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sb_s32", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sb_s64", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sb_u16", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sb_u32", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sb_u64", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sb_vnum_s16", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcnth()": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SB" + ], + [ + "LDNF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sb_vnum_s32", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntw()": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SB" + ], + [ + "LDNF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sb_vnum_s64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntd()": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SB" + ], + [ + "LDNF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sb_vnum_u16", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcnth()": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SB" + ], + [ + "LDNF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sb_vnum_u32", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntw()": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SB" + ], + [ + "LDNF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sb_vnum_u64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntd()": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SB" + ], + [ + "LDNF1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sh_s32", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sh_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sh_u32", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sh_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sh_vnum_s32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntw() * 2": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SH" + ], + [ + "LDNF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sh_vnum_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntd() * 2": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SH" + ], + [ + "LDNF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sh_vnum_u32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntw() * 2": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SH" + ], + [ + "LDNF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sh_vnum_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntd() * 2": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SH" + ], + [ + "LDNF1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sw_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sw_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sw_vnum_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntd() * 4": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SW" + ], + [ + "LDNF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1sw_vnum_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntd() * 4": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1SW" + ], + [ + "LDNF1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1ub_s16", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1ub_s32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1ub_s64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1ub_u16", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1ub_u32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1ub_u64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1ub_vnum_s16", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcnth()": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1B" + ], + [ + "LDNF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1ub_vnum_s32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntw()": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1B" + ], + [ + "LDNF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1ub_vnum_s64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntd()": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1B" + ], + [ + "LDNF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1ub_vnum_u16", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcnth()": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1B" + ], + [ + "LDNF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1ub_vnum_u32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntw()": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1B" + ], + [ + "LDNF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1ub_vnum_u64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntd()": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1B" + ], + [ + "LDNF1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1uh_s32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1uh_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1uh_u32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1uh_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1uh_vnum_s32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntw() * 2": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1H" + ], + [ + "LDNF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1uh_vnum_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntd() * 2": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1H" + ], + [ + "LDNF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1uh_vnum_u32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntw() * 2": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1H" + ], + [ + "LDNF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1uh_vnum_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntd() * 2": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1H" + ], + [ + "LDNF1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1uw_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1uw_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1uw_vnum_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntd() * 4": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1W" + ], + [ + "LDNF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnf1uw_vnum_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "base + vnum * svcntd() * 4": { + "register": "Xptr" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNF1W" + ], + [ + "LDNF1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1[_f16]", + "arguments": [ + "svbool_t pg", + "const float16_t *base" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ], + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_f16]_x2", + "arguments": [ + "svcount_t png", + "float16_t const * rn" + ], + "return_type": { + "value": "svfloat16x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_f16]_x4", + "arguments": [ + "svcount_t png", + "float16_t const * rn" + ], + "return_type": { + "value": "svfloat16x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ], + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_f32]_x2", + "arguments": [ + "svcount_t png", + "float32_t const * rn" + ], + "return_type": { + "value": "svfloat32x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_f32]_x4", + "arguments": [ + "svcount_t png", + "float32_t const * rn" + ], + "return_type": { + "value": "svfloat32x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ], + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_f64]_x2", + "arguments": [ + "svcount_t png", + "float64_t const * rn" + ], + "return_type": { + "value": "svfloat64x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_f64]_x4", + "arguments": [ + "svcount_t png", + "float64_t const * rn" + ], + "return_type": { + "value": "svfloat64x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1[_s16]", + "arguments": [ + "svbool_t pg", + "const int16_t *base" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ], + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_s16]_x2", + "arguments": [ + "svcount_t png", + "int16_t const * rn" + ], + "return_type": { + "value": "svint16x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_s16]_x4", + "arguments": [ + "svcount_t png", + "int16_t const * rn" + ], + "return_type": { + "value": "svint16x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ], + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_s32]_x2", + "arguments": [ + "svcount_t png", + "int32_t const * rn" + ], + "return_type": { + "value": "svint32x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_s32]_x4", + "arguments": [ + "svcount_t png", + "int32_t const * rn" + ], + "return_type": { + "value": "svint32x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ], + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_s64]_x2", + "arguments": [ + "svcount_t png", + "int64_t const * rn" + ], + "return_type": { + "value": "svint64x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_s64]_x4", + "arguments": [ + "svcount_t png", + "int64_t const * rn" + ], + "return_type": { + "value": "svint64x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1[_s8]", + "arguments": [ + "svbool_t pg", + "const int8_t *base" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ], + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_s8]_x2", + "arguments": [ + "svcount_t png", + "int8_t const * rn" + ], + "return_type": { + "value": "svint8x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_s8]_x4", + "arguments": [ + "svcount_t png", + "int8_t const * rn" + ], + "return_type": { + "value": "svint8x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1[_u16]", + "arguments": [ + "svbool_t pg", + "const uint16_t *base" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ], + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_u16]_x2", + "arguments": [ + "svcount_t png", + "uint16_t const * rn" + ], + "return_type": { + "value": "svuint16x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_u16]_x4", + "arguments": [ + "svcount_t png", + "uint16_t const * rn" + ], + "return_type": { + "value": "svuint16x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ], + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_u32]_x2", + "arguments": [ + "svcount_t png", + "uint32_t const * rn" + ], + "return_type": { + "value": "svuint32x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_u32]_x4", + "arguments": [ + "svcount_t png", + "uint32_t const * rn" + ], + "return_type": { + "value": "svuint32x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ], + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_u64]_x2", + "arguments": [ + "svcount_t png", + "uint64_t const * rn" + ], + "return_type": { + "value": "svuint64x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_u64]_x4", + "arguments": [ + "svcount_t png", + "uint64_t const * rn" + ], + "return_type": { + "value": "svuint64x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1[_u8]", + "arguments": [ + "svbool_t pg", + "const uint8_t *base" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ], + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_u8]_x2", + "arguments": [ + "svcount_t png", + "uint8_t const * rn" + ], + "return_type": { + "value": "svuint8x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1[_u8]_x4", + "arguments": [ + "svcount_t png", + "uint8_t const * rn" + ], + "return_type": { + "value": "svuint8x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u32base]_f32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u32base]_index_f32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u32base]_index_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u32base]_index_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u32base]_offset_f32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u32base]_offset_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u32base]_offset_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u32base]_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u32base]_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u64base]_f64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u64base]_index_f64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u64base]_index_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u64base]_index_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u64base]_offset_f64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather_[s64]index[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 8": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather_[s64]index[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 8": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather_[s64]index[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 8": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather_[s64]offset[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather_[s64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather_[s64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather_[u32]offset[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather_[u32]offset[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather_[u32]offset[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather_[u64]index[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 8": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather_[u64]index[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 8": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather_[u64]index[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 8": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather_[u64]offset[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather_[u64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_gather_[u64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1_vnum[_f16]", + "arguments": [ + "svbool_t pg", + "const float16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ], + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_f16]_x2", + "arguments": [ + "svcount_t png", + "float16_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat16x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_f16]_x4", + "arguments": [ + "svcount_t png", + "float16_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat16x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1_vnum[_f32]", + "arguments": [ + "svbool_t pg", + "const float32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ], + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_f32]_x2", + "arguments": [ + "svcount_t png", + "float32_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat32x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_f32]_x4", + "arguments": [ + "svcount_t png", + "float32_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat32x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1_vnum[_f64]", + "arguments": [ + "svbool_t pg", + "const float64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ], + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_f64]_x2", + "arguments": [ + "svcount_t png", + "float64_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat64x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_f64]_x4", + "arguments": [ + "svcount_t png", + "float64_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svfloat64x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1_vnum[_s16]", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ], + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_s16]_x2", + "arguments": [ + "svcount_t png", + "int16_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svint16x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_s16]_x4", + "arguments": [ + "svcount_t png", + "int16_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svint16x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1_vnum[_s32]", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ], + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_s32]_x2", + "arguments": [ + "svcount_t png", + "int32_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svint32x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_s32]_x4", + "arguments": [ + "svcount_t png", + "int32_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svint32x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1_vnum[_s64]", + "arguments": [ + "svbool_t pg", + "const int64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ], + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_s64]_x2", + "arguments": [ + "svcount_t png", + "int64_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svint64x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_s64]_x4", + "arguments": [ + "svcount_t png", + "int64_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svint64x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1_vnum[_s8]", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ], + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_s8]_x2", + "arguments": [ + "svcount_t png", + "int8_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svint8x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MUL", + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_s8]_x4", + "arguments": [ + "svcount_t png", + "int8_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svint8x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MUL", + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1_vnum[_u16]", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ], + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_u16]_x2", + "arguments": [ + "svcount_t png", + "uint16_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_u16]_x4", + "arguments": [ + "svcount_t png", + "uint16_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svuint16x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1_vnum[_u32]", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ], + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_u32]_x2", + "arguments": [ + "svcount_t png", + "uint32_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_u32]_x4", + "arguments": [ + "svcount_t png", + "uint32_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svuint32x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1_vnum[_u64]", + "arguments": [ + "svbool_t pg", + "const uint64_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1D" + ], + [ + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_u64]_x2", + "arguments": [ + "svcount_t png", + "uint64_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_u64]_x4", + "arguments": [ + "svcount_t png", + "uint64_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svuint64x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "LDNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svldnt1_vnum[_u8]", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "int64_t vnum" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ], + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_u8]_x2", + "arguments": [ + "svcount_t png", + "uint8_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svuint8x2_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MUL", + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1_vnum[_u8]_x4", + "arguments": [ + "svcount_t png", + "uint8_t const * rn", + "int64_t vnum" + ], + "return_type": { + "value": "svuint8x4_t" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "vnum": { + "register": "Xreg3" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MUL", + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sb_gather[_u32base]_offset_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sb_gather[_u32base]_offset_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sb_gather[_u32base]_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sb_gather[_u32base]_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sb_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sb_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sb_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sb_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sb_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sb_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sb_gather_[u32]offset_s32", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sb_gather_[u32]offset_u32", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sb_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sb_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int8_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather[_u32base]_index_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather[_u32base]_index_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather[_u32base]_offset_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather[_u32base]_offset_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather[_u32base]_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather[_u32base]_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather[_u64base]_index_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather[_u64base]_index_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather_[s64]index_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 2": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather_[s64]index_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 2": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather_[u32]offset_s32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather_[u32]offset_u32", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather_[u64]index_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 2": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather_[u64]index_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 2": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sh_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int16_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sw_gather[_u64base]_index_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sw_gather[_u64base]_index_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sw_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sw_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sw_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sw_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sw_gather_[s64]index_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 4": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sw_gather_[s64]index_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 4": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sw_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sw_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sw_gather_[u64]index_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 4": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sw_gather_[u64]index_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 4": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sw_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1sw_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const int32_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1SW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1ub_gather[_u32base]_offset_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1ub_gather[_u32base]_offset_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1ub_gather[_u32base]_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1ub_gather[_u32base]_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1ub_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1ub_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1ub_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1ub_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1ub_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1ub_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1ub_gather_[u32]offset_s32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1ub_gather_[u32]offset_u32", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1ub_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1ub_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint8_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather[_u32base]_index_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather[_u32base]_index_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather[_u32base]_offset_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather[_u32base]_offset_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather[_u32base]_s32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather[_u32base]_u32", + "arguments": [ + "svbool_t pg", + "svuint32_t bases" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather[_u64base]_index_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather[_u64base]_index_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather_[s64]index_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 2": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather_[s64]index_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 2": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather_[u32]offset_s32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather_[u32]offset_u32", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint32_t offsets" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather_[u64]index_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 2": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather_[u64]index_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 2": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uh_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint16_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uw_gather[_u64base]_index_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uw_gather[_u64base]_index_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uw_gather[_u64base]_offset_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uw_gather[_u64base]_offset_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uw_gather[_u64base]_s64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uw_gather[_u64base]_u64", + "arguments": [ + "svbool_t pg", + "svuint64_t bases" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uw_gather_[s64]index_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 4": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uw_gather_[s64]index_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 4": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uw_gather_[s64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uw_gather_[s64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uw_gather_[u64]index_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 4": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uw_gather_[u64]index_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices * 4": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uw_gather_[u64]offset_s64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svldnt1uw_gather_[u64]offset_u64", + "arguments": [ + "svbool_t pg", + "const uint32_t *base", + "svuint64_t offsets" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlen[_f16]", + "arguments": [ + "svfloat16_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlen[_f32]", + "arguments": [ + "svfloat32_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlen[_f64]", + "arguments": [ + "svfloat64_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlen[_s16]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlen[_s32]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlen[_s64]", + "arguments": [ + "svint64_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlen[_s8]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlen[_u16]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlen[_u32]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlen[_u64]", + "arguments": [ + "svuint64_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlen[_u8]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "CNTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svlogb[_f16]_m", + "arguments": [ + "svint16_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FLOGB" + ], + [ + "MOVPRFX", + "FLOGB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svlogb[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FLOGB" + ], + [ + "MOVPRFX", + "FLOGB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svlogb[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FLOGB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svlogb[_f32]_m", + "arguments": [ + "svint32_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FLOGB" + ], + [ + "MOVPRFX", + "FLOGB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svlogb[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FLOGB" + ], + [ + "MOVPRFX", + "FLOGB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svlogb[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FLOGB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svlogb[_f64]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FLOGB" + ], + [ + "MOVPRFX", + "FLOGB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svlogb[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FLOGB" + ], + [ + "MOVPRFX", + "FLOGB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svlogb[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FLOGB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ], + [ + "LSLR" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSLR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ], + [ + "LSLR" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSLR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ], + [ + "LSLR" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSLR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ], + [ + "LSLR" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSLR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ], + [ + "LSLR" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSLR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ], + [ + "LSLR" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSLR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ], + [ + "LSLR" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSLR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ], + [ + "LSLR" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSLR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSLR" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSLR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSLR" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSLR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSLR" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSLR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSLR" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSLR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSLR" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSLR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSLR" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSLR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSLR" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSLR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSLR" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSLR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsl_wide[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ], + [ + "LSRR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "LSRR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ], + [ + "LSRR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "LSRR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ], + [ + "LSRR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "LSRR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ], + [ + "LSRR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "LSRR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSRR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "LSRR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSRR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "LSRR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSRR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "LSRR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSRR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "LSRR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ], + [ + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ], + [ + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ], + [ + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSR" + ], + [ + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svlsr_wide[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAD" + ], + [ + "FMAD" + ], + [ + "FMLA" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAD" + ], + [ + "FMAD" + ], + [ + "FMLA" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAD" + ], + [ + "FMAD" + ], + [ + "FMLA" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAD" + ], + [ + "FMAD" + ], + [ + "FMLA" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAD" + ], + [ + "FMAD" + ], + [ + "FMLA" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAD" + ], + [ + "FMAD" + ], + [ + "FMLA" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B[*]|Ztied3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B[*]|Ztied3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B|Ztied3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B|Ztied3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmad[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmatch[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MATCH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmatch[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MATCH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmatch[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MATCH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmatch[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MATCH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAX" + ], + [ + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAX" + ], + [ + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAX" + ], + [ + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAX" + ], + [ + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAX" + ], + [ + "FMAX" + ], + [ + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAX" + ], + [ + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAX" + ], + [ + "FMAX" + ], + [ + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAX" + ], + [ + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAX" + ], + [ + "FMAX" + ], + [ + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ], + [ + "MOVPRFX", + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAX" + ], + [ + "SMAX" + ], + [ + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAX" + ], + [ + "SMAX" + ], + [ + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAX" + ], + [ + "SMAX" + ], + [ + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAX" + ], + [ + "SMAX" + ], + [ + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAX" + ], + [ + "UMAX" + ], + [ + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAX" + ], + [ + "UMAX" + ], + [ + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAX" + ], + [ + "UMAX" + ], + [ + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAX" + ], + [ + "UMAX" + ], + [ + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAX" + ], + [ + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAX" + ], + [ + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAX" + ], + [ + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAX" + ], + [ + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMAX" + ], + [ + "MOVPRFX", + "SMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAX" + ], + [ + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAX" + ], + [ + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAX" + ], + [ + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAX" + ], + [ + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmax[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMAX" + ], + [ + "MOVPRFX", + "UMAX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNM" + ], + [ + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNM" + ], + [ + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNM" + ], + [ + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNM" + ], + [ + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNM" + ], + [ + "FMAXNM" + ], + [ + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNM" + ], + [ + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNM" + ], + [ + "FMAXNM" + ], + [ + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNM" + ], + [ + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNM" + ], + [ + "FMAXNM" + ], + [ + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnm[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ], + [ + "MOVPRFX", + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxnmp[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNMP" + ], + [ + "MOVPRFX", + "FMAXNMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxnmp[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNMP" + ], + [ + "MOVPRFX", + "FMAXNMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxnmp[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNMP" + ], + [ + "MOVPRFX", + "FMAXNMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxnmp[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNMP" + ], + [ + "MOVPRFX", + "FMAXNMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxnmp[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNMP" + ], + [ + "MOVPRFX", + "FMAXNMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxnmp[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNMP" + ], + [ + "MOVPRFX", + "FMAXNMP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnmv[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNMV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnmv[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "float32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNMV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxnmv[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "float64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNMV" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXP" + ], + [ + "MOVPRFX", + "FMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXP" + ], + [ + "MOVPRFX", + "FMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXP" + ], + [ + "MOVPRFX", + "FMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXP" + ], + [ + "MOVPRFX", + "FMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXP" + ], + [ + "MOVPRFX", + "FMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXP" + ], + [ + "MOVPRFX", + "FMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAXP" + ], + [ + "MOVPRFX", + "SMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAXP" + ], + [ + "MOVPRFX", + "SMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAXP" + ], + [ + "MOVPRFX", + "SMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAXP" + ], + [ + "MOVPRFX", + "SMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAXP" + ], + [ + "MOVPRFX", + "SMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAXP" + ], + [ + "MOVPRFX", + "SMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAXP" + ], + [ + "MOVPRFX", + "SMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAXP" + ], + [ + "MOVPRFX", + "SMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAXP" + ], + [ + "MOVPRFX", + "UMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAXP" + ], + [ + "MOVPRFX", + "UMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAXP" + ], + [ + "MOVPRFX", + "UMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAXP" + ], + [ + "MOVPRFX", + "UMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAXP" + ], + [ + "MOVPRFX", + "UMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAXP" + ], + [ + "MOVPRFX", + "UMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAXP" + ], + [ + "MOVPRFX", + "UMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmaxp[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAXP" + ], + [ + "MOVPRFX", + "UMAXP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxv[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxv[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "float32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxv[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "float64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxv[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAXV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxv[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAXV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxv[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAXV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxv[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "int8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMAXV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxv[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAXV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxv[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAXV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxv[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAXV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmaxv[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "uint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMAXV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMIN" + ], + [ + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMIN" + ], + [ + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMIN" + ], + [ + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMIN" + ], + [ + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMIN" + ], + [ + "FMIN" + ], + [ + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMIN" + ], + [ + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMIN" + ], + [ + "FMIN" + ], + [ + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMIN" + ], + [ + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMIN" + ], + [ + "FMIN" + ], + [ + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ], + [ + "MOVPRFX", + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMIN" + ], + [ + "SMIN" + ], + [ + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMIN" + ], + [ + "SMIN" + ], + [ + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMIN" + ], + [ + "SMIN" + ], + [ + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMIN" + ], + [ + "SMIN" + ], + [ + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMIN" + ], + [ + "UMIN" + ], + [ + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMIN" + ], + [ + "UMIN" + ], + [ + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMIN" + ], + [ + "UMIN" + ], + [ + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMIN" + ], + [ + "UMIN" + ], + [ + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMIN" + ], + [ + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMIN" + ], + [ + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMIN" + ], + [ + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMIN" + ], + [ + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMIN" + ], + [ + "MOVPRFX", + "SMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMIN" + ], + [ + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMIN" + ], + [ + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMIN" + ], + [ + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMIN" + ], + [ + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmin[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMIN" + ], + [ + "MOVPRFX", + "UMIN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNM" + ], + [ + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNM" + ], + [ + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNM" + ], + [ + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNM" + ], + [ + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNM" + ], + [ + "FMINNM" + ], + [ + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNM" + ], + [ + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNM" + ], + [ + "FMINNM" + ], + [ + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNM" + ], + [ + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNM" + ], + [ + "FMINNM" + ], + [ + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnm[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ], + [ + "MOVPRFX", + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminnmp[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNMP" + ], + [ + "MOVPRFX", + "FMINNMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminnmp[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNMP" + ], + [ + "MOVPRFX", + "FMINNMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminnmp[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNMP" + ], + [ + "MOVPRFX", + "FMINNMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminnmp[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNMP" + ], + [ + "MOVPRFX", + "FMINNMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminnmp[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNMP" + ], + [ + "MOVPRFX", + "FMINNMP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminnmp[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNMP" + ], + [ + "MOVPRFX", + "FMINNMP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnmv[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNMV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnmv[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "float32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNMV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminnmv[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "float64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNMV" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINP" + ], + [ + "MOVPRFX", + "FMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINP" + ], + [ + "MOVPRFX", + "FMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINP" + ], + [ + "MOVPRFX", + "FMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINP" + ], + [ + "MOVPRFX", + "FMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINP" + ], + [ + "MOVPRFX", + "FMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINP" + ], + [ + "MOVPRFX", + "FMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMINP" + ], + [ + "MOVPRFX", + "SMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMINP" + ], + [ + "MOVPRFX", + "SMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMINP" + ], + [ + "MOVPRFX", + "SMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMINP" + ], + [ + "MOVPRFX", + "SMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMINP" + ], + [ + "MOVPRFX", + "SMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMINP" + ], + [ + "MOVPRFX", + "SMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMINP" + ], + [ + "MOVPRFX", + "SMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMINP" + ], + [ + "MOVPRFX", + "SMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMINP" + ], + [ + "MOVPRFX", + "UMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMINP" + ], + [ + "MOVPRFX", + "UMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMINP" + ], + [ + "MOVPRFX", + "UMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMINP" + ], + [ + "MOVPRFX", + "UMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMINP" + ], + [ + "MOVPRFX", + "UMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMINP" + ], + [ + "MOVPRFX", + "UMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMINP" + ], + [ + "MOVPRFX", + "UMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svminp[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMINP" + ], + [ + "MOVPRFX", + "UMINP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminv[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminv[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "float32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminv[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "float64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminv[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMINV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminv[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMINV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminv[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMINV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminv[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "int8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMINV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminv[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMINV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminv[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMINV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminv[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMINV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svminv[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "uint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMINV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ], + [ + "FMAD" + ], + [ + "FMAD" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMLA" + ], + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ], + [ + "FMAD" + ], + [ + "FMAD" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMLA" + ], + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ], + [ + "FMAD" + ], + [ + "FMAD" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMLA" + ], + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ], + [ + "FMAD" + ], + [ + "FMAD" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMLA" + ], + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ], + [ + "FMAD" + ], + [ + "FMAD" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMLA" + ], + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ], + [ + "FMAD" + ], + [ + "FMAD" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMLA" + ], + [ + "MOVPRFX", + "FMAD" + ], + [ + "MOVPRFX", + "FMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B[*]|Ztied3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B[*]|Ztied3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B|Ztied3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B|Ztied3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MAD" + ], + [ + "MAD" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLA" + ], + [ + "MOVPRFX", + "MAD" + ], + [ + "MOVPRFX", + "MAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla_lane[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla_lane[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmla_lane[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ], + [ + "MOVPRFX", + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmla_lane[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmla_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmla_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "svint64_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmla_lane[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmla_lane[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmla_lane[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLA" + ], + [ + "MOVPRFX", + "MLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLALB" + ], + [ + "MOVPRFX", + "FMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb[_n_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLALB" + ], + [ + "MOVPRFX", + "FMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLALB" + ], + [ + "MOVPRFX", + "SMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLALB" + ], + [ + "MOVPRFX", + "SMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLALB" + ], + [ + "MOVPRFX", + "SMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLALB" + ], + [ + "MOVPRFX", + "UMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLALB" + ], + [ + "MOVPRFX", + "UMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLALB" + ], + [ + "MOVPRFX", + "UMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb[_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLALB" + ], + [ + "MOVPRFX", + "SMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLALB" + ], + [ + "MOVPRFX", + "SMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLALB" + ], + [ + "MOVPRFX", + "SMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLALB" + ], + [ + "MOVPRFX", + "UMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLALB" + ], + [ + "MOVPRFX", + "UMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLALB" + ], + [ + "MOVPRFX", + "UMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb_lane[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLALB" + ], + [ + "MOVPRFX", + "FMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLALB" + ], + [ + "MOVPRFX", + "SMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLALB" + ], + [ + "MOVPRFX", + "SMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb_lane[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2", + "svuint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLALB" + ], + [ + "MOVPRFX", + "UMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalb_lane[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2", + "svuint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLALB" + ], + [ + "MOVPRFX", + "UMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLALT" + ], + [ + "MOVPRFX", + "FMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt[_n_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLALT" + ], + [ + "MOVPRFX", + "FMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLALT" + ], + [ + "MOVPRFX", + "SMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLALT" + ], + [ + "MOVPRFX", + "SMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLALT" + ], + [ + "MOVPRFX", + "SMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLALT" + ], + [ + "MOVPRFX", + "UMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLALT" + ], + [ + "MOVPRFX", + "UMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLALT" + ], + [ + "MOVPRFX", + "UMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt[_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLALT" + ], + [ + "MOVPRFX", + "SMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLALT" + ], + [ + "MOVPRFX", + "SMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLALT" + ], + [ + "MOVPRFX", + "SMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLALT" + ], + [ + "MOVPRFX", + "UMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLALT" + ], + [ + "MOVPRFX", + "UMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLALT" + ], + [ + "MOVPRFX", + "UMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt_lane[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLALT" + ], + [ + "MOVPRFX", + "FMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLALT" + ], + [ + "MOVPRFX", + "SMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLALT" + ], + [ + "MOVPRFX", + "SMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt_lane[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2", + "svuint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLALT" + ], + [ + "MOVPRFX", + "UMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlalt_lane[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2", + "svuint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLALT" + ], + [ + "MOVPRFX", + "UMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ], + [ + "FMSB" + ], + [ + "FMSB" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMLS" + ], + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ], + [ + "FMSB" + ], + [ + "FMSB" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMLS" + ], + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ], + [ + "FMSB" + ], + [ + "FMSB" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMLS" + ], + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ], + [ + "FMSB" + ], + [ + "FMSB" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMLS" + ], + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ], + [ + "FMSB" + ], + [ + "FMSB" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMLS" + ], + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ], + [ + "FMSB" + ], + [ + "FMSB" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMLS" + ], + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B[*]|Ztied3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B[*]|Ztied3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B|Ztied3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B|Ztied3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls_lane[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls_lane[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmls_lane[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmls_lane[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmls_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmls_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "svint64_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmls_lane[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmls_lane[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmls_lane[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MLS" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLSLB" + ], + [ + "MOVPRFX", + "FMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb[_n_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLSLB" + ], + [ + "MOVPRFX", + "FMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLSLB" + ], + [ + "MOVPRFX", + "SMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLSLB" + ], + [ + "MOVPRFX", + "SMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLSLB" + ], + [ + "MOVPRFX", + "SMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLSLB" + ], + [ + "MOVPRFX", + "UMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLSLB" + ], + [ + "MOVPRFX", + "UMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLSLB" + ], + [ + "MOVPRFX", + "UMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb[_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLSLB" + ], + [ + "MOVPRFX", + "SMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLSLB" + ], + [ + "MOVPRFX", + "SMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLSLB" + ], + [ + "MOVPRFX", + "SMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLSLB" + ], + [ + "MOVPRFX", + "UMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLSLB" + ], + [ + "MOVPRFX", + "UMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLSLB" + ], + [ + "MOVPRFX", + "UMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb_lane[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLSLB" + ], + [ + "MOVPRFX", + "FMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLSLB" + ], + [ + "MOVPRFX", + "SMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLSLB" + ], + [ + "MOVPRFX", + "SMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb_lane[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2", + "svuint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLSLB" + ], + [ + "MOVPRFX", + "UMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslb_lane[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2", + "svuint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLSLB" + ], + [ + "MOVPRFX", + "UMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLSLT" + ], + [ + "MOVPRFX", + "FMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt[_n_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLSLT" + ], + [ + "MOVPRFX", + "FMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLSLT" + ], + [ + "MOVPRFX", + "SMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLSLT" + ], + [ + "MOVPRFX", + "SMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLSLT" + ], + [ + "MOVPRFX", + "SMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLSLT" + ], + [ + "MOVPRFX", + "UMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLSLT" + ], + [ + "MOVPRFX", + "UMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLSLT" + ], + [ + "MOVPRFX", + "UMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt[_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLSLT" + ], + [ + "MOVPRFX", + "SMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLSLT" + ], + [ + "MOVPRFX", + "SMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLSLT" + ], + [ + "MOVPRFX", + "SMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLSLT" + ], + [ + "MOVPRFX", + "UMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLSLT" + ], + [ + "MOVPRFX", + "UMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLSLT" + ], + [ + "MOVPRFX", + "UMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt_lane[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat16_t op2", + "svfloat16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLSLT" + ], + [ + "MOVPRFX", + "FMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLSLT" + ], + [ + "MOVPRFX", + "SMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMLSLT" + ], + [ + "MOVPRFX", + "SMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt_lane[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2", + "svuint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLSLT" + ], + [ + "MOVPRFX", + "UMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmlslt_lane[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2", + "svuint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMLSLT" + ], + [ + "MOVPRFX", + "UMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmmla[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMMLA" + ], + [ + "MOVPRFX", + "FMMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmmla[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMMLA" + ], + [ + "MOVPRFX", + "FMMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmmla[_s32]", + "arguments": [ + "svint32_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMMLA" + ], + [ + "MOVPRFX", + "SMMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmmla[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMMLA" + ], + [ + "MOVPRFX", + "UMMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmov[_b]_z", + "arguments": [ + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Pop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "AND" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmovlb[_s16]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSHLLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmovlb[_s32]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSHLLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmovlb[_s64]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSHLLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmovlb[_u16]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USHLLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmovlb[_u32]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USHLLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmovlb[_u64]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USHLLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmovlt[_s16]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSHLLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmovlt[_s32]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSHLLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmovlt[_s64]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSHLLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmovlt[_u16]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USHLLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmovlt[_u32]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USHLLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmovlt[_u64]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USHLLT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMSB" + ], + [ + "FMSB" + ], + [ + "FMLS" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMSB" + ], + [ + "FMSB" + ], + [ + "FMLS" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMSB" + ], + [ + "FMSB" + ], + [ + "FMLS" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMSB" + ], + [ + "FMSB" + ], + [ + "FMLS" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMSB" + ], + [ + "FMSB" + ], + [ + "FMLS" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMSB" + ], + [ + "FMSB" + ], + [ + "FMLS" + ], + [ + "MOVPRFX", + "FMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMSB" + ], + [ + "MOVPRFX", + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B[*]|Ztied3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B[*]|Ztied3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B|Ztied3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "op3": { + "register": "Zop3.B|Ztied3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MSB" + ], + [ + "MSB" + ], + [ + "MLS" + ], + [ + "MOVPRFX", + "MSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmsb[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MSB" + ], + [ + "MOVPRFX", + "MLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ], + [ + "FMUL" + ], + [ + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ], + [ + "FMUL" + ], + [ + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ], + [ + "FMUL" + ], + [ + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ], + [ + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ], + [ + "FMUL" + ], + [ + "FMUL" + ], + [ + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ], + [ + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ], + [ + "FMUL" + ], + [ + "FMUL" + ], + [ + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ], + [ + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ], + [ + "FMUL" + ], + [ + "FMUL" + ], + [ + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ], + [ + "MOVPRFX", + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ], + [ + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "MUL" + ], + [ + "MOVPRFX", + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul_lane[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul_lane[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmul_lane[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmul_lane[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmul_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmul_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmul_lane[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmul_lane[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmul_lane[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULH" + ], + [ + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULH" + ], + [ + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULH" + ], + [ + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULH" + ], + [ + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULH" + ], + [ + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULH" + ], + [ + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULH" + ], + [ + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULH" + ], + [ + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULH" + ], + [ + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULH" + ], + [ + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULH" + ], + [ + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULH" + ], + [ + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SMULH" + ], + [ + "MOVPRFX", + "SMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULH" + ], + [ + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULH" + ], + [ + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULH" + ], + [ + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULH" + ], + [ + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulh[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UMULH" + ], + [ + "MOVPRFX", + "UMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullb[_n_s16]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullb[_n_s32]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullb[_n_s64]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullb[_n_u16]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullb[_n_u32]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullb[_n_u64]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullb[_s16]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullb[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullb[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullb[_u16]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullb[_u32]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullb[_u64]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullb_lane[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullb_lane[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullb_lane[_u32]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullb_lane[_u64]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullt[_n_s16]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullt[_n_s32]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullt[_n_s64]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullt[_n_u16]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullt[_n_u32]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullt[_n_u64]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullt[_s16]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullt[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullt[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullt[_u16]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullt[_u32]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullt[_u64]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullt_lane[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullt_lane[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullt_lane[_u32]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svmullt_lane[_u64]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ], + [ + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ], + [ + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ], + [ + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ], + [ + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ], + [ + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ], + [ + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svmulx[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FMULX" + ], + [ + "MOVPRFX", + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnand[_b]_z", + "arguments": [ + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NAND" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnbsl[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NBSL" + ], + [ + "MOVPRFX", + "NBSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnbsl[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NBSL" + ], + [ + "MOVPRFX", + "NBSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnbsl[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NBSL" + ], + [ + "MOVPRFX", + "NBSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnbsl[_n_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NBSL" + ], + [ + "MOVPRFX", + "NBSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnbsl[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NBSL" + ], + [ + "MOVPRFX", + "NBSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnbsl[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NBSL" + ], + [ + "MOVPRFX", + "NBSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnbsl[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NBSL" + ], + [ + "MOVPRFX", + "NBSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnbsl[_n_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NBSL" + ], + [ + "MOVPRFX", + "NBSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnbsl[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NBSL" + ], + [ + "MOVPRFX", + "NBSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnbsl[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NBSL" + ], + [ + "MOVPRFX", + "NBSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnbsl[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NBSL" + ], + [ + "MOVPRFX", + "NBSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnbsl[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NBSL" + ], + [ + "MOVPRFX", + "NBSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnbsl[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "svuint16_t op3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NBSL" + ], + [ + "MOVPRFX", + "NBSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnbsl[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NBSL" + ], + [ + "MOVPRFX", + "NBSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnbsl[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NBSL" + ], + [ + "MOVPRFX", + "NBSL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnbsl[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NBSL" + ], + [ + "MOVPRFX", + "NBSL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_f16]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNEG" + ], + [ + "MOVPRFX", + "FNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNEG" + ], + [ + "MOVPRFX", + "FNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_f32]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNEG" + ], + [ + "MOVPRFX", + "FNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNEG" + ], + [ + "MOVPRFX", + "FNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_f64]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNEG" + ], + [ + "MOVPRFX", + "FNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNEG" + ], + [ + "MOVPRFX", + "FNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_s16]_m", + "arguments": [ + "svint16_t inactive", + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NEG" + ], + [ + "MOVPRFX", + "NEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NEG" + ], + [ + "MOVPRFX", + "NEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "NEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_s32]_m", + "arguments": [ + "svint32_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NEG" + ], + [ + "MOVPRFX", + "NEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NEG" + ], + [ + "MOVPRFX", + "NEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "NEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_s64]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NEG" + ], + [ + "MOVPRFX", + "NEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NEG" + ], + [ + "MOVPRFX", + "NEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "NEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_s8]_m", + "arguments": [ + "svint8_t inactive", + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NEG" + ], + [ + "MOVPRFX", + "NEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NEG" + ], + [ + "MOVPRFX", + "NEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svneg[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "NEG" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMAD" + ], + [ + "FNMAD" + ], + [ + "FNMLA" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMAD" + ], + [ + "FNMAD" + ], + [ + "FNMLA" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMAD" + ], + [ + "FNMAD" + ], + [ + "FNMLA" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMAD" + ], + [ + "FNMAD" + ], + [ + "FNMLA" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMAD" + ], + [ + "FNMAD" + ], + [ + "FNMLA" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMAD" + ], + [ + "FNMAD" + ], + [ + "FNMLA" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmad[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnmatch[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NMATCH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnmatch[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NMATCH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnmatch[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NMATCH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svnmatch[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NMATCH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLA" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLA" + ], + [ + "FNMAD" + ], + [ + "FNMAD" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMLA" + ], + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLA" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLA" + ], + [ + "FNMAD" + ], + [ + "FNMAD" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMLA" + ], + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLA" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLA" + ], + [ + "FNMAD" + ], + [ + "FNMAD" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMLA" + ], + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLA" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLA" + ], + [ + "FNMAD" + ], + [ + "FNMAD" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMLA" + ], + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLA" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLA" + ], + [ + "FNMAD" + ], + [ + "FNMAD" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMLA" + ], + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLA" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLA" + ], + [ + "FNMAD" + ], + [ + "FNMAD" + ], + [ + "MOVPRFX", + "FNMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmla[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMLA" + ], + [ + "MOVPRFX", + "FNMAD" + ], + [ + "MOVPRFX", + "FNMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLS" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLS" + ], + [ + "FNMSB" + ], + [ + "FNMSB" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMLS" + ], + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLS" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLS" + ], + [ + "FNMSB" + ], + [ + "FNMSB" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMLS" + ], + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLS" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLS" + ], + [ + "FNMSB" + ], + [ + "FNMSB" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMLS" + ], + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLS" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLS" + ], + [ + "FNMSB" + ], + [ + "FNMSB" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMLS" + ], + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLS" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLS" + ], + [ + "FNMSB" + ], + [ + "FNMSB" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMLS" + ], + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLS" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMLS" + ], + [ + "FNMSB" + ], + [ + "FNMSB" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmls[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMLS" + ], + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H|Ztied3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMSB" + ], + [ + "FNMSB" + ], + [ + "FNMLS" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "svfloat16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S|Ztied3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMSB" + ], + [ + "FNMSB" + ], + [ + "FNMLS" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "svfloat32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D|Ztied3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMSB" + ], + [ + "FNMSB" + ], + [ + "FNMLS" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "svfloat64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "op3": { + "register": "Zop3.H[*]|Ztied3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMSB" + ], + [ + "FNMSB" + ], + [ + "FNMLS" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2", + "float16_t op3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "op3": { + "register": "Zop3.S[*]|Ztied3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMSB" + ], + [ + "FNMSB" + ], + [ + "FNMLS" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2", + "float32_t op3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "op3": { + "register": "Zop3.D[*]|Ztied3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FNMSB" + ], + [ + "FNMSB" + ], + [ + "FNMLS" + ], + [ + "MOVPRFX", + "FNMSB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnmsb[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2", + "float64_t op3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMSB" + ], + [ + "MOVPRFX", + "FNMLS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnor[_b]_z", + "arguments": [ + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_b]_z", + "arguments": [ + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Pop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "EOR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_s16]_m", + "arguments": [ + "svint16_t inactive", + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOT" + ], + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOT" + ], + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_s32]_m", + "arguments": [ + "svint32_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOT" + ], + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOT" + ], + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_s64]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOT" + ], + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOT" + ], + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_s8]_m", + "arguments": [ + "svint8_t inactive", + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOT" + ], + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOT" + ], + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_u16]_m", + "arguments": [ + "svuint16_t inactive", + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOT" + ], + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOT" + ], + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_u32]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOT" + ], + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOT" + ], + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_u64]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOT" + ], + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOT" + ], + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_u8]_m", + "arguments": [ + "svuint8_t inactive", + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOT" + ], + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOT" + ], + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svnot[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "NOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorn[_b]_z", + "arguments": [ + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_b]_z", + "arguments": [ + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORR" + ], + [ + "ORR" + ], + [ + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorr[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "ORR" + ], + [ + "MOVPRFX", + "ORR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorv[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorv[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorv[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorv[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "int8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorv[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorv[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorv[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svorv[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "uint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ORV" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpext_lane_c16", + "arguments": [ + "svcount_t pnn", + "uint64_t imm" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "imm": { + "immediate": "imm1" + }, + "pnn": { + "register": "PNreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpext_lane_c16_x2", + "arguments": [ + "svcount_t pnn", + "uint64_t imm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "imm": { + "immediate": "imm1" + }, + "pnn": { + "register": "PNreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpext_lane_c32", + "arguments": [ + "svcount_t pnn", + "uint64_t imm" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "imm": { + "immediate": "imm1" + }, + "pnn": { + "register": "PNreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpext_lane_c32_x2", + "arguments": [ + "svcount_t pnn", + "uint64_t imm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "imm": { + "immediate": "imm1" + }, + "pnn": { + "register": "PNreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpext_lane_c64", + "arguments": [ + "svcount_t pnn", + "uint64_t imm" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "imm": { + "immediate": "imm1" + }, + "pnn": { + "register": "PNreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpext_lane_c64_x2", + "arguments": [ + "svcount_t pnn", + "uint64_t imm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "imm": { + "immediate": "imm1" + }, + "pnn": { + "register": "PNreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpext_lane_c8", + "arguments": [ + "svcount_t pnn", + "uint64_t imm" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "imm": { + "immediate": "imm1" + }, + "pnn": { + "register": "PNreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpext_lane_c8_x2", + "arguments": [ + "svcount_t pnn", + "uint64_t imm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "imm": { + "immediate": "imm1" + }, + "pnn": { + "register": "PNreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svpfalse[_b]", + "arguments": [], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PFALSE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpfalse_c", + "arguments": [], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PFALSE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svpfirst[_b]", + "arguments": [ + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Ptied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PFIRST" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmul[_n_u8]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmul[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullb[_n_u16]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullb[_n_u64]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullb[_u16]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullb[_u64]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullb_pair[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullb_pair[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullb_pair[_n_u8]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullb_pair[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullb_pair[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullb_pair[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullt[_n_u16]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullt[_n_u64]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullt[_u16]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullt[_u64]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullt_pair[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullt_pair[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullt_pair[_n_u8]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullt_pair[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullt_pair[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpmullt_pair[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svpnext_b16", + "arguments": [ + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Ptied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PNEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svpnext_b32", + "arguments": [ + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Ptied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PNEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svpnext_b64", + "arguments": [ + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Ptied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PNEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svpnext_b8", + "arguments": [ + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Ptied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PNEXT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfb", + "arguments": [ + "svbool_t pg", + "const void *base", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFB" + ], + [ + "PRFB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfb_gather[_u32base]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfb_gather[_u32base]_offset", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFB" + ], + [ + "PRFB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfb_gather[_u64base]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfb_gather[_u64base]_offset", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFB" + ], + [ + "PRFB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfb_gather_[s32]offset", + "arguments": [ + "svbool_t pg", + "const void *base", + "svint32_t offsets", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfb_gather_[s64]offset", + "arguments": [ + "svbool_t pg", + "const void *base", + "svint64_t offsets", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfb_gather_[u32]offset", + "arguments": [ + "svbool_t pg", + "const void *base", + "svuint32_t offsets", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfb_gather_[u64]offset", + "arguments": [ + "svbool_t pg", + "const void *base", + "svuint64_t offsets", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfb_vnum", + "arguments": [ + "svbool_t pg", + "const void *base", + "int64_t vnum", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFB" + ], + [ + "PRFB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfd", + "arguments": [ + "svbool_t pg", + "const void *base", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFD" + ], + [ + "PRFD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfd_gather[_u32base]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfd_gather[_u32base]_index", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFD" + ], + [ + "PRFB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfd_gather[_u64base]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfd_gather[_u64base]_index", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFD" + ], + [ + "PRFB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfd_gather_[s32]index", + "arguments": [ + "svbool_t pg", + "const void *base", + "svint32_t indices", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfd_gather_[s64]index", + "arguments": [ + "svbool_t pg", + "const void *base", + "svint64_t indices", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfd_gather_[u32]index", + "arguments": [ + "svbool_t pg", + "const void *base", + "svuint32_t indices", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfd_gather_[u64]index", + "arguments": [ + "svbool_t pg", + "const void *base", + "svuint64_t indices", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfd_vnum", + "arguments": [ + "svbool_t pg", + "const void *base", + "int64_t vnum", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFD" + ], + [ + "PRFD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfh", + "arguments": [ + "svbool_t pg", + "const void *base", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFH" + ], + [ + "PRFH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfh_gather[_u32base]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfh_gather[_u32base]_index", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFH" + ], + [ + "PRFB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfh_gather[_u64base]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfh_gather[_u64base]_index", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFH" + ], + [ + "PRFB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfh_gather_[s32]index", + "arguments": [ + "svbool_t pg", + "const void *base", + "svint32_t indices", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfh_gather_[s64]index", + "arguments": [ + "svbool_t pg", + "const void *base", + "svint64_t indices", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfh_gather_[u32]index", + "arguments": [ + "svbool_t pg", + "const void *base", + "svuint32_t indices", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfh_gather_[u64]index", + "arguments": [ + "svbool_t pg", + "const void *base", + "svuint64_t indices", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfh_vnum", + "arguments": [ + "svbool_t pg", + "const void *base", + "int64_t vnum", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFH" + ], + [ + "PRFH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfw", + "arguments": [ + "svbool_t pg", + "const void *base", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFW" + ], + [ + "PRFW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfw_gather[_u32base]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfw_gather[_u32base]_index", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFW" + ], + [ + "PRFB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfw_gather[_u64base]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfw_gather[_u64base]_index", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFW" + ], + [ + "PRFB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfw_gather_[s32]index", + "arguments": [ + "svbool_t pg", + "const void *base", + "svint32_t indices", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfw_gather_[s64]index", + "arguments": [ + "svbool_t pg", + "const void *base", + "svint64_t indices", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfw_gather_[u32]index", + "arguments": [ + "svbool_t pg", + "const void *base", + "svuint32_t indices", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfw_gather_[u64]index", + "arguments": [ + "svbool_t pg", + "const void *base", + "svuint64_t indices", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svprfw_vnum", + "arguments": [ + "svbool_t pg", + "const void *base", + "int64_t vnum", + "enum svprfop op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PRFW" + ], + [ + "PRFW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpsel_lane_b16", + "arguments": [ + "svbool_t pn", + "svbool_t pm", + "uint32_t idx" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "idx": { + "index": "[Wreg1, imm1]" + }, + "pm": { + "register": "Preg3" + }, + "pn": { + "register": "Preg2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PSEL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpsel_lane_b32", + "arguments": [ + "svbool_t pn", + "svbool_t pm", + "uint32_t idx" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "idx": { + "index": "[Wreg1, imm1]" + }, + "pm": { + "register": "Preg3" + }, + "pn": { + "register": "Preg2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PSEL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpsel_lane_b64", + "arguments": [ + "svbool_t pn", + "svbool_t pm", + "uint32_t idx" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "idx": { + "index": "[Wreg1, imm1]" + }, + "pm": { + "register": "Preg3" + }, + "pn": { + "register": "Preg2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PSEL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpsel_lane_b8", + "arguments": [ + "svbool_t pn", + "svbool_t pm", + "uint32_t idx" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "idx": { + "index": "[Wreg1, imm1]" + }, + "pm": { + "register": "Preg3" + }, + "pn": { + "register": "Preg2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PSEL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpsel_lane_c16", + "arguments": [ + "svcount_t pn", + "svbool_t pm", + "uint32_t idx" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "idx": { + "index": "[Wreg1, imm1]" + }, + "pm": { + "register": "Preg3" + }, + "pn": { + "register": "Preg2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PSEL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpsel_lane_c32", + "arguments": [ + "svcount_t pn", + "svbool_t pm", + "uint32_t idx" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "idx": { + "index": "[Wreg1, imm1]" + }, + "pm": { + "register": "Preg3" + }, + "pn": { + "register": "Preg2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PSEL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpsel_lane_c64", + "arguments": [ + "svcount_t pn", + "svbool_t pm", + "uint32_t idx" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "idx": { + "index": "[Wreg1, imm1]" + }, + "pm": { + "register": "Preg3" + }, + "pn": { + "register": "Preg2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PSEL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svpsel_lane_c8", + "arguments": [ + "svcount_t pn", + "svbool_t pm", + "uint32_t idx" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "idx": { + "index": "[Wreg1, imm1]" + }, + "pm": { + "register": "Preg3" + }, + "pn": { + "register": "Preg2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PSEL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svptest_any", + "arguments": [ + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "bool" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svptest_first", + "arguments": [ + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "bool" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svptest_last", + "arguments": [ + "svbool_t pg", + "svbool_t op" + ], + "return_type": { + "value": "bool" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svptrue_b16", + "arguments": [], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PTRUE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svptrue_b32", + "arguments": [], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PTRUE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svptrue_b64", + "arguments": [], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PTRUE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svptrue_b8", + "arguments": [], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PTRUE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svptrue_c16", + "arguments": [], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PTRUE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svptrue_c32", + "arguments": [], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PTRUE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svptrue_c64", + "arguments": [], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PTRUE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svptrue_c8", + "arguments": [], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PTRUE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svptrue_pat_b16", + "arguments": [ + "enum svpattern pattern" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PTRUE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svptrue_pat_b32", + "arguments": [ + "enum svpattern pattern" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PTRUE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svptrue_pat_b64", + "arguments": [ + "enum svpattern pattern" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PTRUE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svptrue_pat_b8", + "arguments": [ + "enum svpattern pattern" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PTRUE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqabs[_s16]_m", + "arguments": [ + "svint16_t inactive", + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQABS" + ], + [ + "MOVPRFX", + "SQABS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqabs[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQABS" + ], + [ + "MOVPRFX", + "SQABS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqabs[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQABS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqabs[_s32]_m", + "arguments": [ + "svint32_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQABS" + ], + [ + "MOVPRFX", + "SQABS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqabs[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQABS" + ], + [ + "MOVPRFX", + "SQABS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqabs[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQABS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqabs[_s64]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQABS" + ], + [ + "MOVPRFX", + "SQABS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqabs[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQABS" + ], + [ + "MOVPRFX", + "SQABS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqabs[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQABS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqabs[_s8]_m", + "arguments": [ + "svint8_t inactive", + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQABS" + ], + [ + "MOVPRFX", + "SQABS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqabs[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQABS" + ], + [ + "MOVPRFX", + "SQABS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqabs[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQABS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqadd[_n_s16]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "SQSUB" + ], + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "MOVPRFX", + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "SQSUB" + ], + [ + "SQADD" + ], + [ + "SQADD" + ], + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQADD" + ], + [ + "MOVPRFX", + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqadd[_n_s32]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "SQSUB" + ], + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "MOVPRFX", + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "SQSUB" + ], + [ + "SQADD" + ], + [ + "SQADD" + ], + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQADD" + ], + [ + "MOVPRFX", + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqadd[_n_s64]", + "arguments": [ + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "SQSUB" + ], + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "MOVPRFX", + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "SQSUB" + ], + [ + "SQADD" + ], + [ + "SQADD" + ], + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQADD" + ], + [ + "MOVPRFX", + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqadd[_n_s8]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "SQSUB" + ], + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "MOVPRFX", + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "SQSUB" + ], + [ + "SQADD" + ], + [ + "SQADD" + ], + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQADD" + ], + [ + "MOVPRFX", + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqadd[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "MOVPRFX", + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "UQADD" + ], + [ + "UQADD" + ], + [ + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQADD" + ], + [ + "MOVPRFX", + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqadd[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "MOVPRFX", + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "UQADD" + ], + [ + "UQADD" + ], + [ + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQADD" + ], + [ + "MOVPRFX", + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqadd[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "MOVPRFX", + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "UQADD" + ], + [ + "UQADD" + ], + [ + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQADD" + ], + [ + "MOVPRFX", + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqadd[_n_u8]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "MOVPRFX", + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "UQADD" + ], + [ + "UQADD" + ], + [ + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQADD" + ], + [ + "MOVPRFX", + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqadd[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "MOVPRFX", + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "SQADD" + ], + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQADD" + ], + [ + "MOVPRFX", + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqadd[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "MOVPRFX", + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "SQADD" + ], + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQADD" + ], + [ + "MOVPRFX", + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqadd[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "MOVPRFX", + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "SQADD" + ], + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQADD" + ], + [ + "MOVPRFX", + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqadd[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "MOVPRFX", + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "SQADD" + ], + [ + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQADD" + ], + [ + "MOVPRFX", + "SQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqadd[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "MOVPRFX", + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "UQADD" + ], + [ + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQADD" + ], + [ + "MOVPRFX", + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqadd[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "MOVPRFX", + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "UQADD" + ], + [ + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQADD" + ], + [ + "MOVPRFX", + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqadd[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "MOVPRFX", + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "UQADD" + ], + [ + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQADD" + ], + [ + "MOVPRFX", + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqadd[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "MOVPRFX", + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "UQADD" + ], + [ + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqadd[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQADD" + ], + [ + "MOVPRFX", + "UQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqcadd[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQCADD" + ], + [ + "MOVPRFX", + "SQCADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqcadd[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQCADD" + ], + [ + "MOVPRFX", + "SQCADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqcadd[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQCADD" + ], + [ + "MOVPRFX", + "SQCADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqcadd[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQCADD" + ], + [ + "MOVPRFX", + "SQCADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqcvtn_s16[_s32_x2]", + "arguments": [ + "svint32x2_t zn" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "zn": { + "Z multi-vector": "{ Zreg2.S, Zreg3.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQCVTN" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqcvtn_u16[_s32_x2]", + "arguments": [ + "svint32x2_t zn" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "zn": { + "Z multi-vector": "{ Zreg2.S, Zreg3.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQCVTUN" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqcvtn_u16[_u32_x2]", + "arguments": [ + "svuint32x2_t zn" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "zn": { + "Z multi-vector": "{ Zreg2.S, Zreg3.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQCVTN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecb[_n_s32]", + "arguments": [ + "int32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecb[_n_s64]", + "arguments": [ + "int64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecb[_n_u32]", + "arguments": [ + "uint32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecb[_n_u64]", + "arguments": [ + "uint64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecb_pat[_n_s32]", + "arguments": [ + "int32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecb_pat[_n_s64]", + "arguments": [ + "int64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecb_pat[_n_u32]", + "arguments": [ + "uint32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecb_pat[_n_u64]", + "arguments": [ + "uint64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecd[_n_s32]", + "arguments": [ + "int32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecd[_n_s64]", + "arguments": [ + "int64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecd[_n_u32]", + "arguments": [ + "uint32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecd[_n_u64]", + "arguments": [ + "uint64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecd[_s64]", + "arguments": [ + "svint64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.D|Ztied.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECD" + ], + [ + "MOVPRFX", + "SQDECD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecd[_u64]", + "arguments": [ + "svuint64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.D|Ztied.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECD" + ], + [ + "MOVPRFX", + "UQDECD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecd_pat[_n_s32]", + "arguments": [ + "int32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecd_pat[_n_s64]", + "arguments": [ + "int64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecd_pat[_n_u32]", + "arguments": [ + "uint32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecd_pat[_n_u64]", + "arguments": [ + "uint64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecd_pat[_s64]", + "arguments": [ + "svint64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.D|Ztied.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECD" + ], + [ + "MOVPRFX", + "SQDECD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecd_pat[_u64]", + "arguments": [ + "svuint64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.D|Ztied.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECD" + ], + [ + "MOVPRFX", + "UQDECD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdech[_n_s32]", + "arguments": [ + "int32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdech[_n_s64]", + "arguments": [ + "int64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdech[_n_u32]", + "arguments": [ + "uint32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdech[_n_u64]", + "arguments": [ + "uint64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdech[_s16]", + "arguments": [ + "svint16_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.H|Ztied.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECH" + ], + [ + "MOVPRFX", + "SQDECH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdech[_u16]", + "arguments": [ + "svuint16_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.H|Ztied.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECH" + ], + [ + "MOVPRFX", + "UQDECH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdech_pat[_n_s32]", + "arguments": [ + "int32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdech_pat[_n_s64]", + "arguments": [ + "int64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdech_pat[_n_u32]", + "arguments": [ + "uint32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdech_pat[_n_u64]", + "arguments": [ + "uint64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdech_pat[_s16]", + "arguments": [ + "svint16_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.H|Ztied.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECH" + ], + [ + "MOVPRFX", + "SQDECH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdech_pat[_u16]", + "arguments": [ + "svuint16_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.H|Ztied.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECH" + ], + [ + "MOVPRFX", + "UQDECH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_n_s32]_b16", + "arguments": [ + "int32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Wtied" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_n_s32]_b32", + "arguments": [ + "int32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Wtied" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_n_s32]_b64", + "arguments": [ + "int32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Wtied" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_n_s32]_b8", + "arguments": [ + "int32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Wtied" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_n_s64]_b16", + "arguments": [ + "int64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Xtied" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_n_s64]_b32", + "arguments": [ + "int64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Xtied" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_n_s64]_b64", + "arguments": [ + "int64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Xtied" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_n_s64]_b8", + "arguments": [ + "int64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Xtied" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_n_u32]_b16", + "arguments": [ + "uint32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Wtied" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_n_u32]_b32", + "arguments": [ + "uint32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Wtied" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_n_u32]_b64", + "arguments": [ + "uint32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Wtied" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_n_u32]_b8", + "arguments": [ + "uint32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Wtied" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_n_u64]_b16", + "arguments": [ + "uint64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Xtied" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_n_u64]_b32", + "arguments": [ + "uint64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Xtied" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_n_u64]_b64", + "arguments": [ + "uint64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Xtied" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_n_u64]_b8", + "arguments": [ + "uint64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Xtied" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_s16]", + "arguments": [ + "svint16_t op", + "svbool_t pg" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECP" + ], + [ + "MOVPRFX", + "SQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_s32]", + "arguments": [ + "svint32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECP" + ], + [ + "MOVPRFX", + "SQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_s64]", + "arguments": [ + "svint64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECP" + ], + [ + "MOVPRFX", + "SQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_u16]", + "arguments": [ + "svuint16_t op", + "svbool_t pg" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECP" + ], + [ + "MOVPRFX", + "UQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_u32]", + "arguments": [ + "svuint32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECP" + ], + [ + "MOVPRFX", + "UQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecp[_u64]", + "arguments": [ + "svuint64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECP" + ], + [ + "MOVPRFX", + "UQDECP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecw[_n_s32]", + "arguments": [ + "int32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecw[_n_s64]", + "arguments": [ + "int64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecw[_n_u32]", + "arguments": [ + "uint32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecw[_n_u64]", + "arguments": [ + "uint64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecw[_s32]", + "arguments": [ + "svint32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.S|Ztied.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECW" + ], + [ + "MOVPRFX", + "SQDECW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecw[_u32]", + "arguments": [ + "svuint32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.S|Ztied.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECW" + ], + [ + "MOVPRFX", + "UQDECW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecw_pat[_n_s32]", + "arguments": [ + "int32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecw_pat[_n_s64]", + "arguments": [ + "int64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecw_pat[_n_u32]", + "arguments": [ + "uint32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecw_pat[_n_u64]", + "arguments": [ + "uint64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecw_pat[_s32]", + "arguments": [ + "svint32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.S|Ztied.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDECW" + ], + [ + "MOVPRFX", + "SQDECW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqdecw_pat[_u32]", + "arguments": [ + "svuint32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.S|Ztied.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQDECW" + ], + [ + "MOVPRFX", + "UQDECW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalb[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALB" + ], + [ + "MOVPRFX", + "SQDMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalb[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALB" + ], + [ + "MOVPRFX", + "SQDMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalb[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALB" + ], + [ + "MOVPRFX", + "SQDMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalb[_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALB" + ], + [ + "MOVPRFX", + "SQDMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalb[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALB" + ], + [ + "MOVPRFX", + "SQDMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalb[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALB" + ], + [ + "MOVPRFX", + "SQDMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalb_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALB" + ], + [ + "MOVPRFX", + "SQDMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalb_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALB" + ], + [ + "MOVPRFX", + "SQDMLALB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalbt[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALBT" + ], + [ + "MOVPRFX", + "SQDMLALBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalbt[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALBT" + ], + [ + "MOVPRFX", + "SQDMLALBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalbt[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALBT" + ], + [ + "MOVPRFX", + "SQDMLALBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalbt[_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALBT" + ], + [ + "MOVPRFX", + "SQDMLALBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalbt[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALBT" + ], + [ + "MOVPRFX", + "SQDMLALBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalbt[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALBT" + ], + [ + "MOVPRFX", + "SQDMLALBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalt[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALT" + ], + [ + "MOVPRFX", + "SQDMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalt[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALT" + ], + [ + "MOVPRFX", + "SQDMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalt[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALT" + ], + [ + "MOVPRFX", + "SQDMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalt[_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALT" + ], + [ + "MOVPRFX", + "SQDMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalt[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALT" + ], + [ + "MOVPRFX", + "SQDMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalt[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALT" + ], + [ + "MOVPRFX", + "SQDMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalt_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALT" + ], + [ + "MOVPRFX", + "SQDMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlalt_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLALT" + ], + [ + "MOVPRFX", + "SQDMLALT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslb[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLB" + ], + [ + "MOVPRFX", + "SQDMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslb[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLB" + ], + [ + "MOVPRFX", + "SQDMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslb[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLB" + ], + [ + "MOVPRFX", + "SQDMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslb[_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLB" + ], + [ + "MOVPRFX", + "SQDMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslb[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLB" + ], + [ + "MOVPRFX", + "SQDMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslb[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLB" + ], + [ + "MOVPRFX", + "SQDMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslb_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLB" + ], + [ + "MOVPRFX", + "SQDMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslb_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLB" + ], + [ + "MOVPRFX", + "SQDMLSLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslbt[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLBT" + ], + [ + "MOVPRFX", + "SQDMLSLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslbt[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLBT" + ], + [ + "MOVPRFX", + "SQDMLSLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslbt[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLBT" + ], + [ + "MOVPRFX", + "SQDMLSLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslbt[_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLBT" + ], + [ + "MOVPRFX", + "SQDMLSLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslbt[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLBT" + ], + [ + "MOVPRFX", + "SQDMLSLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslbt[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLBT" + ], + [ + "MOVPRFX", + "SQDMLSLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslt[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLT" + ], + [ + "MOVPRFX", + "SQDMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslt[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLT" + ], + [ + "MOVPRFX", + "SQDMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslt[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLT" + ], + [ + "MOVPRFX", + "SQDMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslt[_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLT" + ], + [ + "MOVPRFX", + "SQDMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslt[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLT" + ], + [ + "MOVPRFX", + "SQDMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslt[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLT" + ], + [ + "MOVPRFX", + "SQDMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslt_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLT" + ], + [ + "MOVPRFX", + "SQDMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmlslt_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMLSLT" + ], + [ + "MOVPRFX", + "SQDMLSLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmulh[_n_s16]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmulh[_n_s32]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmulh[_n_s64]", + "arguments": [ + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmulh[_n_s8]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmulh[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmulh[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmulh[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmulh[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmulh_lane[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmulh_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmulh_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmullb[_n_s16]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmullb[_n_s32]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmullb[_n_s64]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmullb[_s16]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmullb[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmullb[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmullb_lane[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmullb_lane[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmullt[_n_s16]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmullt[_n_s32]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmullt[_n_s64]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmullt[_s16]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmullt[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmullt[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmullt_lane[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqdmullt_lane[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQDMULLT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincb[_n_s32]", + "arguments": [ + "int32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincb[_n_s64]", + "arguments": [ + "int64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincb[_n_u32]", + "arguments": [ + "uint32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincb[_n_u64]", + "arguments": [ + "uint64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincb_pat[_n_s32]", + "arguments": [ + "int32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincb_pat[_n_s64]", + "arguments": [ + "int64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincb_pat[_n_u32]", + "arguments": [ + "uint32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincb_pat[_n_u64]", + "arguments": [ + "uint64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincd[_n_s32]", + "arguments": [ + "int32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincd[_n_s64]", + "arguments": [ + "int64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincd[_n_u32]", + "arguments": [ + "uint32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincd[_n_u64]", + "arguments": [ + "uint64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincd[_s64]", + "arguments": [ + "svint64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.D|Ztied.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCD" + ], + [ + "MOVPRFX", + "SQINCD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincd[_u64]", + "arguments": [ + "svuint64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.D|Ztied.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCD" + ], + [ + "MOVPRFX", + "UQINCD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincd_pat[_n_s32]", + "arguments": [ + "int32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincd_pat[_n_s64]", + "arguments": [ + "int64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincd_pat[_n_u32]", + "arguments": [ + "uint32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincd_pat[_n_u64]", + "arguments": [ + "uint64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincd_pat[_s64]", + "arguments": [ + "svint64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.D|Ztied.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCD" + ], + [ + "MOVPRFX", + "SQINCD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincd_pat[_u64]", + "arguments": [ + "svuint64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.D|Ztied.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCD" + ], + [ + "MOVPRFX", + "UQINCD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqinch[_n_s32]", + "arguments": [ + "int32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqinch[_n_s64]", + "arguments": [ + "int64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqinch[_n_u32]", + "arguments": [ + "uint32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqinch[_n_u64]", + "arguments": [ + "uint64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqinch[_s16]", + "arguments": [ + "svint16_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.H|Ztied.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCH" + ], + [ + "MOVPRFX", + "SQINCH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqinch[_u16]", + "arguments": [ + "svuint16_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.H|Ztied.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCH" + ], + [ + "MOVPRFX", + "UQINCH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqinch_pat[_n_s32]", + "arguments": [ + "int32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqinch_pat[_n_s64]", + "arguments": [ + "int64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqinch_pat[_n_u32]", + "arguments": [ + "uint32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqinch_pat[_n_u64]", + "arguments": [ + "uint64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqinch_pat[_s16]", + "arguments": [ + "svint16_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.H|Ztied.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCH" + ], + [ + "MOVPRFX", + "SQINCH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqinch_pat[_u16]", + "arguments": [ + "svuint16_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.H|Ztied.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCH" + ], + [ + "MOVPRFX", + "UQINCH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_n_s32]_b16", + "arguments": [ + "int32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Wtied" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_n_s32]_b32", + "arguments": [ + "int32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Wtied" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_n_s32]_b64", + "arguments": [ + "int32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Wtied" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_n_s32]_b8", + "arguments": [ + "int32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Wtied" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_n_s64]_b16", + "arguments": [ + "int64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Xtied" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_n_s64]_b32", + "arguments": [ + "int64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Xtied" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_n_s64]_b64", + "arguments": [ + "int64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Xtied" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_n_s64]_b8", + "arguments": [ + "int64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Xtied" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_n_u32]_b16", + "arguments": [ + "uint32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Wtied" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_n_u32]_b32", + "arguments": [ + "uint32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Wtied" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_n_u32]_b64", + "arguments": [ + "uint32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Wtied" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_n_u32]_b8", + "arguments": [ + "uint32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Wtied" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_n_u64]_b16", + "arguments": [ + "uint64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Xtied" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_n_u64]_b32", + "arguments": [ + "uint64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Xtied" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_n_u64]_b64", + "arguments": [ + "uint64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Xtied" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_n_u64]_b8", + "arguments": [ + "uint64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Xtied" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_s16]", + "arguments": [ + "svint16_t op", + "svbool_t pg" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCP" + ], + [ + "MOVPRFX", + "SQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_s32]", + "arguments": [ + "svint32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCP" + ], + [ + "MOVPRFX", + "SQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_s64]", + "arguments": [ + "svint64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCP" + ], + [ + "MOVPRFX", + "SQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_u16]", + "arguments": [ + "svuint16_t op", + "svbool_t pg" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCP" + ], + [ + "MOVPRFX", + "UQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_u32]", + "arguments": [ + "svuint32_t op", + "svbool_t pg" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCP" + ], + [ + "MOVPRFX", + "UQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincp[_u64]", + "arguments": [ + "svuint64_t op", + "svbool_t pg" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCP" + ], + [ + "MOVPRFX", + "UQINCP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincw[_n_s32]", + "arguments": [ + "int32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincw[_n_s64]", + "arguments": [ + "int64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincw[_n_u32]", + "arguments": [ + "uint32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincw[_n_u64]", + "arguments": [ + "uint64_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincw[_s32]", + "arguments": [ + "svint32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.S|Ztied.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCW" + ], + [ + "MOVPRFX", + "SQINCW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincw[_u32]", + "arguments": [ + "svuint32_t op", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.S|Ztied.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCW" + ], + [ + "MOVPRFX", + "UQINCW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincw_pat[_n_s32]", + "arguments": [ + "int32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincw_pat[_n_s64]", + "arguments": [ + "int64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincw_pat[_n_u32]", + "arguments": [ + "uint32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Wtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincw_pat[_n_u64]", + "arguments": [ + "uint64_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Xtied" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincw_pat[_s32]", + "arguments": [ + "svint32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.S|Ztied.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQINCW" + ], + [ + "MOVPRFX", + "SQINCW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqincw_pat[_u32]", + "arguments": [ + "svuint32_t op", + "enum svpattern pattern", + "uint64_t imm_factor" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm_factor": { + "minimum": 1, + "maximum": 16 + }, + "op": { + "register": "Zop.S|Ztied.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQINCW" + ], + [ + "MOVPRFX", + "UQINCW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqneg[_s16]_m", + "arguments": [ + "svint16_t inactive", + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQNEG" + ], + [ + "MOVPRFX", + "SQNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqneg[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQNEG" + ], + [ + "MOVPRFX", + "SQNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqneg[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqneg[_s32]_m", + "arguments": [ + "svint32_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQNEG" + ], + [ + "MOVPRFX", + "SQNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqneg[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQNEG" + ], + [ + "MOVPRFX", + "SQNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqneg[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqneg[_s64]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQNEG" + ], + [ + "MOVPRFX", + "SQNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqneg[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQNEG" + ], + [ + "MOVPRFX", + "SQNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqneg[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqneg[_s8]_m", + "arguments": [ + "svint8_t inactive", + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQNEG" + ], + [ + "MOVPRFX", + "SQNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqneg[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQNEG" + ], + [ + "MOVPRFX", + "SQNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqneg[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQNEG" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdcmlah[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDCMLAH" + ], + [ + "MOVPRFX", + "SQRDCMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdcmlah[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDCMLAH" + ], + [ + "MOVPRFX", + "SQRDCMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdcmlah[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "svint64_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDCMLAH" + ], + [ + "MOVPRFX", + "SQRDCMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdcmlah[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "svint8_t op3", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDCMLAH" + ], + [ + "MOVPRFX", + "SQRDCMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdcmlah_lane[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDCMLAH" + ], + [ + "MOVPRFX", + "SQRDCMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdcmlah_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_index", + "uint64_t imm_rotation" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDCMLAH" + ], + [ + "MOVPRFX", + "SQRDCMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlah[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLAH" + ], + [ + "MOVPRFX", + "SQRDMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlah[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLAH" + ], + [ + "MOVPRFX", + "SQRDMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlah[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLAH" + ], + [ + "MOVPRFX", + "SQRDMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlah[_n_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLAH" + ], + [ + "MOVPRFX", + "SQRDMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlah[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLAH" + ], + [ + "MOVPRFX", + "SQRDMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlah[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLAH" + ], + [ + "MOVPRFX", + "SQRDMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlah[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLAH" + ], + [ + "MOVPRFX", + "SQRDMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlah[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLAH" + ], + [ + "MOVPRFX", + "SQRDMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlah_lane[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLAH" + ], + [ + "MOVPRFX", + "SQRDMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlah_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLAH" + ], + [ + "MOVPRFX", + "SQRDMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlah_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "svint64_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLAH" + ], + [ + "MOVPRFX", + "SQRDMLAH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlsh[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLSH" + ], + [ + "MOVPRFX", + "SQRDMLSH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlsh[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLSH" + ], + [ + "MOVPRFX", + "SQRDMLSH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlsh[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLSH" + ], + [ + "MOVPRFX", + "SQRDMLSH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlsh[_n_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLSH" + ], + [ + "MOVPRFX", + "SQRDMLSH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlsh[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLSH" + ], + [ + "MOVPRFX", + "SQRDMLSH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlsh[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLSH" + ], + [ + "MOVPRFX", + "SQRDMLSH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlsh[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "svint64_t op3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLSH" + ], + [ + "MOVPRFX", + "SQRDMLSH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlsh[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLSH" + ], + [ + "MOVPRFX", + "SQRDMLSH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlsh_lane[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "svint16_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLSH" + ], + [ + "MOVPRFX", + "SQRDMLSH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlsh_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "svint32_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLSH" + ], + [ + "MOVPRFX", + "SQRDMLSH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmlsh_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "svint64_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMLSH" + ], + [ + "MOVPRFX", + "SQRDMLSH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmulh[_n_s16]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmulh[_n_s32]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmulh[_n_s64]", + "arguments": [ + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmulh[_n_s8]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmulh[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmulh[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmulh[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmulh[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmulh_lane[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmulh_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrdmulh_lane[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 1 + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRDMULH" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "SRSHR" + ], + [ + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "SRSHR" + ], + [ + "SQRSHL" + ], + [ + "SQRSHLR" + ], + [ + "MOVPRFX", + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSHL" + ], + [ + "MOVPRFX", + "SRSHR" + ], + [ + "MOVPRFX", + "SQRSHL" + ], + [ + "MOVPRFX", + "SQRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "SRSHR" + ], + [ + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "SRSHR" + ], + [ + "SQRSHL" + ], + [ + "SQRSHLR" + ], + [ + "MOVPRFX", + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSHL" + ], + [ + "MOVPRFX", + "SRSHR" + ], + [ + "MOVPRFX", + "SQRSHL" + ], + [ + "MOVPRFX", + "SQRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "SRSHR" + ], + [ + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "SRSHR" + ], + [ + "SQRSHL" + ], + [ + "SQRSHLR" + ], + [ + "MOVPRFX", + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSHL" + ], + [ + "MOVPRFX", + "SRSHR" + ], + [ + "MOVPRFX", + "SQRSHL" + ], + [ + "MOVPRFX", + "SQRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "SRSHR" + ], + [ + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "SRSHR" + ], + [ + "SQRSHL" + ], + [ + "SQRSHLR" + ], + [ + "MOVPRFX", + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSHL" + ], + [ + "MOVPRFX", + "SRSHR" + ], + [ + "MOVPRFX", + "SQRSHL" + ], + [ + "MOVPRFX", + "SQRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "URSHR" + ], + [ + "UQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "URSHR" + ], + [ + "UQRSHL" + ], + [ + "UQRSHLR" + ], + [ + "MOVPRFX", + "UQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSHL" + ], + [ + "MOVPRFX", + "URSHR" + ], + [ + "MOVPRFX", + "UQRSHL" + ], + [ + "MOVPRFX", + "UQRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "URSHR" + ], + [ + "UQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "URSHR" + ], + [ + "UQRSHL" + ], + [ + "UQRSHLR" + ], + [ + "MOVPRFX", + "UQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSHL" + ], + [ + "MOVPRFX", + "URSHR" + ], + [ + "MOVPRFX", + "UQRSHL" + ], + [ + "MOVPRFX", + "UQRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "URSHR" + ], + [ + "UQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "URSHR" + ], + [ + "UQRSHL" + ], + [ + "UQRSHLR" + ], + [ + "MOVPRFX", + "UQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSHL" + ], + [ + "MOVPRFX", + "URSHR" + ], + [ + "MOVPRFX", + "UQRSHL" + ], + [ + "MOVPRFX", + "UQRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "URSHR" + ], + [ + "UQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "URSHR" + ], + [ + "UQRSHL" + ], + [ + "UQRSHLR" + ], + [ + "MOVPRFX", + "UQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSHL" + ], + [ + "MOVPRFX", + "URSHR" + ], + [ + "MOVPRFX", + "UQRSHL" + ], + [ + "MOVPRFX", + "UQRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHL" + ], + [ + "MOVPRFX", + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHL" + ], + [ + "SQRSHLR" + ], + [ + "MOVPRFX", + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQRSHL" + ], + [ + "MOVPRFX", + "SQRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHL" + ], + [ + "MOVPRFX", + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHL" + ], + [ + "SQRSHLR" + ], + [ + "MOVPRFX", + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQRSHL" + ], + [ + "MOVPRFX", + "SQRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHL" + ], + [ + "MOVPRFX", + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHL" + ], + [ + "SQRSHLR" + ], + [ + "MOVPRFX", + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQRSHL" + ], + [ + "MOVPRFX", + "SQRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHL" + ], + [ + "MOVPRFX", + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHL" + ], + [ + "SQRSHLR" + ], + [ + "MOVPRFX", + "SQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQRSHL" + ], + [ + "MOVPRFX", + "SQRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQRSHL" + ], + [ + "MOVPRFX", + "UQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQRSHL" + ], + [ + "UQRSHLR" + ], + [ + "MOVPRFX", + "UQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQRSHL" + ], + [ + "MOVPRFX", + "UQRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQRSHL" + ], + [ + "MOVPRFX", + "UQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQRSHL" + ], + [ + "UQRSHLR" + ], + [ + "MOVPRFX", + "UQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQRSHL" + ], + [ + "MOVPRFX", + "UQRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQRSHL" + ], + [ + "MOVPRFX", + "UQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQRSHL" + ], + [ + "UQRSHLR" + ], + [ + "MOVPRFX", + "UQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQRSHL" + ], + [ + "MOVPRFX", + "UQRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQRSHL" + ], + [ + "MOVPRFX", + "UQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQRSHL" + ], + [ + "UQRSHLR" + ], + [ + "MOVPRFX", + "UQRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshl[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQRSHL" + ], + [ + "MOVPRFX", + "UQRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrn[_n]_s16[_s32_x2]", + "arguments": [ + "svint32x2_t zn", + "uint64_t imm" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm": { + "immediate": "imm1" + }, + "zn": { + "Z multi-vector": "{ Zreg2.S, Zreg3.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHRN" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrn[_n]_u16[_u32_x2]", + "arguments": [ + "svuint32x2_t zn", + "uint64_t imm" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm": { + "immediate": "imm1" + }, + "zn": { + "Z multi-vector": "{ Zreg2.S, Zreg3.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQRSHRN" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrnb[_n_s16]", + "arguments": [ + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrnb[_n_s32]", + "arguments": [ + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrnb[_n_s64]", + "arguments": [ + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrnb[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQRSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrnb[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQRSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrnb[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQRSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrnt[_n_s16]", + "arguments": [ + "svint8_t even", + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrnt[_n_s32]", + "arguments": [ + "svint16_t even", + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrnt[_n_s64]", + "arguments": [ + "svint32_t even", + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrnt[_n_u16]", + "arguments": [ + "svuint8_t even", + "svuint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQRSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrnt[_n_u32]", + "arguments": [ + "svuint16_t even", + "svuint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQRSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrnt[_n_u64]", + "arguments": [ + "svuint32_t even", + "svuint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQRSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrun[_n]_u16[_s32_x2]", + "arguments": [ + "svint32x2_t zn", + "uint64_t imm" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm": { + "immediate": "imm1" + }, + "zn": { + "Z multi-vector": "{ Zreg2.S, Zreg3.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHRUN" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrunb[_n_s16]", + "arguments": [ + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHRUNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrunb[_n_s32]", + "arguments": [ + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHRUNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrunb[_n_s64]", + "arguments": [ + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHRUNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrunt[_n_s16]", + "arguments": [ + "svuint8_t even", + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHRUNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrunt[_n_s32]", + "arguments": [ + "svuint16_t even", + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHRUNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqrshrunt[_n_s64]", + "arguments": [ + "svuint32_t even", + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQRSHRUNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "ASR" + ], + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "ASR" + ], + [ + "SQSHL" + ], + [ + "SQSHLR" + ], + [ + "MOVPRFX", + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSHL" + ], + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "SQSHL" + ], + [ + "MOVPRFX", + "SQSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "ASR" + ], + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "ASR" + ], + [ + "SQSHL" + ], + [ + "SQSHLR" + ], + [ + "MOVPRFX", + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSHL" + ], + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "SQSHL" + ], + [ + "MOVPRFX", + "SQSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "ASR" + ], + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "ASR" + ], + [ + "SQSHL" + ], + [ + "SQSHLR" + ], + [ + "MOVPRFX", + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSHL" + ], + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "SQSHL" + ], + [ + "MOVPRFX", + "SQSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "ASR" + ], + [ + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "ASR" + ], + [ + "SQSHL" + ], + [ + "SQSHLR" + ], + [ + "MOVPRFX", + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSHL" + ], + [ + "MOVPRFX", + "ASR" + ], + [ + "MOVPRFX", + "SQSHL" + ], + [ + "MOVPRFX", + "SQSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "LSR" + ], + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "LSR" + ], + [ + "UQSHL" + ], + [ + "UQSHLR" + ], + [ + "MOVPRFX", + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSHL" + ], + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "UQSHL" + ], + [ + "MOVPRFX", + "UQSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "LSR" + ], + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "LSR" + ], + [ + "UQSHL" + ], + [ + "UQSHLR" + ], + [ + "MOVPRFX", + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSHL" + ], + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "UQSHL" + ], + [ + "MOVPRFX", + "UQSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "LSR" + ], + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "LSR" + ], + [ + "UQSHL" + ], + [ + "UQSHLR" + ], + [ + "MOVPRFX", + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSHL" + ], + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "UQSHL" + ], + [ + "MOVPRFX", + "UQSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "LSR" + ], + [ + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "LSR" + ], + [ + "UQSHL" + ], + [ + "UQSHLR" + ], + [ + "MOVPRFX", + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSHL" + ], + [ + "MOVPRFX", + "LSR" + ], + [ + "MOVPRFX", + "UQSHL" + ], + [ + "MOVPRFX", + "UQSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "MOVPRFX", + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "SQSHLR" + ], + [ + "MOVPRFX", + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSHL" + ], + [ + "MOVPRFX", + "SQSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "MOVPRFX", + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "SQSHLR" + ], + [ + "MOVPRFX", + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSHL" + ], + [ + "MOVPRFX", + "SQSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "MOVPRFX", + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "SQSHLR" + ], + [ + "MOVPRFX", + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSHL" + ], + [ + "MOVPRFX", + "SQSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "MOVPRFX", + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHL" + ], + [ + "SQSHLR" + ], + [ + "MOVPRFX", + "SQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSHL" + ], + [ + "MOVPRFX", + "SQSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "MOVPRFX", + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "UQSHLR" + ], + [ + "MOVPRFX", + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSHL" + ], + [ + "MOVPRFX", + "UQSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "MOVPRFX", + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "UQSHLR" + ], + [ + "MOVPRFX", + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSHL" + ], + [ + "MOVPRFX", + "UQSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "MOVPRFX", + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "UQSHLR" + ], + [ + "MOVPRFX", + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSHL" + ], + [ + "MOVPRFX", + "UQSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "MOVPRFX", + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHL" + ], + [ + "UQSHLR" + ], + [ + "MOVPRFX", + "UQSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshl[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSHL" + ], + [ + "MOVPRFX", + "UQSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshlu[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 15 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHLU" + ], + [ + "MOVPRFX", + "SQSHLU" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshlu[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 15 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHLU" + ], + [ + "MOVPRFX", + "SQSHLU" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshlu[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 15 + }, + "op1": { + "register": "Zop1.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSHLU" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshlu[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 31 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHLU" + ], + [ + "MOVPRFX", + "SQSHLU" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshlu[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 31 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHLU" + ], + [ + "MOVPRFX", + "SQSHLU" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshlu[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 31 + }, + "op1": { + "register": "Zop1.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSHLU" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshlu[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 63 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHLU" + ], + [ + "MOVPRFX", + "SQSHLU" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshlu[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 63 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHLU" + ], + [ + "MOVPRFX", + "SQSHLU" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshlu[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 63 + }, + "op1": { + "register": "Zop1.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSHLU" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshlu[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHLU" + ], + [ + "MOVPRFX", + "SQSHLU" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshlu[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHLU" + ], + [ + "MOVPRFX", + "SQSHLU" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshlu[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSHLU" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrnb[_n_s16]", + "arguments": [ + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrnb[_n_s32]", + "arguments": [ + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrnb[_n_s64]", + "arguments": [ + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrnb[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrnb[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrnb[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrnt[_n_s16]", + "arguments": [ + "svint8_t even", + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrnt[_n_s32]", + "arguments": [ + "svint16_t even", + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrnt[_n_s64]", + "arguments": [ + "svint32_t even", + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrnt[_n_u16]", + "arguments": [ + "svuint8_t even", + "svuint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrnt[_n_u32]", + "arguments": [ + "svuint16_t even", + "svuint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrnt[_n_u64]", + "arguments": [ + "svuint32_t even", + "svuint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrunb[_n_s16]", + "arguments": [ + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHRUNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrunb[_n_s32]", + "arguments": [ + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHRUNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrunb[_n_s64]", + "arguments": [ + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHRUNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrunt[_n_s16]", + "arguments": [ + "svuint8_t even", + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHRUNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrunt[_n_s32]", + "arguments": [ + "svuint16_t even", + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHRUNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqshrunt[_n_s64]", + "arguments": [ + "svuint32_t even", + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSHRUNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqsub[_n_s16]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "SQADD" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "MOVPRFX", + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "SQADD" + ], + [ + "SQSUB" + ], + [ + "SQSUBR" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSUB" + ], + [ + "MOVPRFX", + "SQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqsub[_n_s32]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "SQADD" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "MOVPRFX", + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "SQADD" + ], + [ + "SQSUB" + ], + [ + "SQSUBR" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSUB" + ], + [ + "MOVPRFX", + "SQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqsub[_n_s64]", + "arguments": [ + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "SQADD" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "MOVPRFX", + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "SQADD" + ], + [ + "SQSUB" + ], + [ + "SQSUBR" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSUB" + ], + [ + "MOVPRFX", + "SQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqsub[_n_s8]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "SQADD" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "MOVPRFX", + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "SQADD" + ], + [ + "SQSUB" + ], + [ + "SQSUBR" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSUB" + ], + [ + "MOVPRFX", + "SQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqsub[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "MOVPRFX", + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "UQSUB" + ], + [ + "UQSUBR" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSUB" + ], + [ + "MOVPRFX", + "UQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqsub[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "MOVPRFX", + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "UQSUB" + ], + [ + "UQSUBR" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSUB" + ], + [ + "MOVPRFX", + "UQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqsub[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "MOVPRFX", + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "UQSUB" + ], + [ + "UQSUBR" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSUB" + ], + [ + "MOVPRFX", + "UQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqsub[_n_u8]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "MOVPRFX", + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "UQSUB" + ], + [ + "UQSUBR" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSUB" + ], + [ + "MOVPRFX", + "UQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqsub[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "MOVPRFX", + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "SQSUBR" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSUB" + ], + [ + "MOVPRFX", + "SQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqsub[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "MOVPRFX", + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "SQSUBR" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSUB" + ], + [ + "MOVPRFX", + "SQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqsub[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "MOVPRFX", + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "SQSUBR" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSUB" + ], + [ + "MOVPRFX", + "SQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqsub[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "MOVPRFX", + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUB" + ], + [ + "SQSUBR" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSUB" + ], + [ + "MOVPRFX", + "SQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqsub[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "MOVPRFX", + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "UQSUBR" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSUB" + ], + [ + "MOVPRFX", + "UQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqsub[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "MOVPRFX", + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "UQSUBR" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSUB" + ], + [ + "MOVPRFX", + "UQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqsub[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "MOVPRFX", + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "UQSUBR" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSUB" + ], + [ + "MOVPRFX", + "UQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svqsub[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "MOVPRFX", + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUB" + ], + [ + "UQSUBR" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsub[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSUB" + ], + [ + "MOVPRFX", + "UQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUBR" + ], + [ + "MOVPRFX", + "SQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUBR" + ], + [ + "SQSUB" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSUBR" + ], + [ + "MOVPRFX", + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUBR" + ], + [ + "MOVPRFX", + "SQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUBR" + ], + [ + "SQSUB" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSUBR" + ], + [ + "MOVPRFX", + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUBR" + ], + [ + "MOVPRFX", + "SQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUBR" + ], + [ + "SQSUB" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSUBR" + ], + [ + "MOVPRFX", + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUBR" + ], + [ + "MOVPRFX", + "SQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUBR" + ], + [ + "SQSUB" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSUBR" + ], + [ + "MOVPRFX", + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUBR" + ], + [ + "MOVPRFX", + "UQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUBR" + ], + [ + "UQSUB" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSUBR" + ], + [ + "MOVPRFX", + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUBR" + ], + [ + "MOVPRFX", + "UQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUBR" + ], + [ + "UQSUB" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSUBR" + ], + [ + "MOVPRFX", + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUBR" + ], + [ + "MOVPRFX", + "UQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUBR" + ], + [ + "UQSUB" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSUBR" + ], + [ + "MOVPRFX", + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUBR" + ], + [ + "MOVPRFX", + "UQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUBR" + ], + [ + "UQSUB" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSUBR" + ], + [ + "MOVPRFX", + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUBR" + ], + [ + "MOVPRFX", + "SQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUBR" + ], + [ + "SQSUB" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSUBR" + ], + [ + "MOVPRFX", + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUBR" + ], + [ + "MOVPRFX", + "SQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUBR" + ], + [ + "SQSUB" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSUBR" + ], + [ + "MOVPRFX", + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUBR" + ], + [ + "MOVPRFX", + "SQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUBR" + ], + [ + "SQSUB" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSUBR" + ], + [ + "MOVPRFX", + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUBR" + ], + [ + "MOVPRFX", + "SQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQSUBR" + ], + [ + "SQSUB" + ], + [ + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SQSUBR" + ], + [ + "MOVPRFX", + "SQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUBR" + ], + [ + "MOVPRFX", + "UQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUBR" + ], + [ + "UQSUB" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSUBR" + ], + [ + "MOVPRFX", + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUBR" + ], + [ + "MOVPRFX", + "UQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUBR" + ], + [ + "UQSUB" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSUBR" + ], + [ + "MOVPRFX", + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUBR" + ], + [ + "MOVPRFX", + "UQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUBR" + ], + [ + "UQSUB" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSUBR" + ], + [ + "MOVPRFX", + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUBR" + ], + [ + "MOVPRFX", + "UQSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQSUBR" + ], + [ + "UQSUB" + ], + [ + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqsubr[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "UQSUBR" + ], + [ + "MOVPRFX", + "UQSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtnb[_s16]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQXTNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtnb[_s32]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQXTNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtnb[_s64]", + "arguments": [ + "svint64_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQXTNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtnb[_u16]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQXTNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtnb[_u32]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQXTNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtnb[_u64]", + "arguments": [ + "svuint64_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQXTNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtnt[_s16]", + "arguments": [ + "svint8_t even", + "svint16_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQXTNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtnt[_s32]", + "arguments": [ + "svint16_t even", + "svint32_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQXTNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtnt[_s64]", + "arguments": [ + "svint32_t even", + "svint64_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op": { + "register": "Zop.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQXTNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtnt[_u16]", + "arguments": [ + "svuint8_t even", + "svuint16_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQXTNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtnt[_u32]", + "arguments": [ + "svuint16_t even", + "svuint32_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQXTNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtnt[_u64]", + "arguments": [ + "svuint32_t even", + "svuint64_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op": { + "register": "Zop.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQXTNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtunb[_s16]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQXTUNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtunb[_s32]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQXTUNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtunb[_s64]", + "arguments": [ + "svint64_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQXTUNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtunt[_s16]", + "arguments": [ + "svuint8_t even", + "svint16_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQXTUNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtunt[_s32]", + "arguments": [ + "svuint16_t even", + "svint32_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQXTUNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svqxtunt[_s64]", + "arguments": [ + "svuint32_t even", + "svint64_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op": { + "register": "Zop.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQXTUNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnb[_n_s16]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnb[_n_s32]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnb[_n_s64]", + "arguments": [ + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnb[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnb[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnb[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnb[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnb[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnb[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnb[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnb[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnb[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnt[_n_s16]", + "arguments": [ + "svint8_t even", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnt[_n_s32]", + "arguments": [ + "svint16_t even", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnt[_n_s64]", + "arguments": [ + "svint32_t even", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnt[_n_u16]", + "arguments": [ + "svuint8_t even", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnt[_n_u32]", + "arguments": [ + "svuint16_t even", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnt[_n_u64]", + "arguments": [ + "svuint32_t even", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnt[_s16]", + "arguments": [ + "svint8_t even", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnt[_s32]", + "arguments": [ + "svint16_t even", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnt[_s64]", + "arguments": [ + "svint32_t even", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnt[_u16]", + "arguments": [ + "svuint8_t even", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnt[_u32]", + "arguments": [ + "svuint16_t even", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svraddhnt[_u64]", + "arguments": [ + "svuint32_t even", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RADDHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrax1[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RAX1" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrax1[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RAX1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_s16]_m", + "arguments": [ + "svint16_t inactive", + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RBIT" + ], + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RBIT" + ], + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_s32]_m", + "arguments": [ + "svint32_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RBIT" + ], + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RBIT" + ], + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_s64]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RBIT" + ], + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RBIT" + ], + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_s8]_m", + "arguments": [ + "svint8_t inactive", + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RBIT" + ], + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RBIT" + ], + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_u16]_m", + "arguments": [ + "svuint16_t inactive", + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RBIT" + ], + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RBIT" + ], + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_u32]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RBIT" + ], + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RBIT" + ], + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_u64]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RBIT" + ], + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RBIT" + ], + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_u8]_m", + "arguments": [ + "svuint8_t inactive", + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.B|Ztied.B" + }, + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RBIT" + ], + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B|Ztied.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RBIT" + ], + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrbit[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "RBIT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrdffr", + "arguments": [], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDFFR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrdffr_z", + "arguments": [ + "svbool_t pg" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDFFR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrecpe[_f16]", + "arguments": [ + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRECPE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrecpe[_f32]", + "arguments": [ + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRECPE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrecpe[_f64]", + "arguments": [ + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRECPE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrecpe[_u32]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URECPE" + ], + [ + "MOVPRFX", + "URECPE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrecpe[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URECPE" + ], + [ + "MOVPRFX", + "URECPE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrecpe[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URECPE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrecps[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRECPS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrecps[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRECPS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrecps[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRECPS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrecpx[_f16]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRECPX" + ], + [ + "MOVPRFX", + "FRECPX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrecpx[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRECPX" + ], + [ + "MOVPRFX", + "FRECPX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrecpx[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRECPX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrecpx[_f32]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRECPX" + ], + [ + "MOVPRFX", + "FRECPX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrecpx[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRECPX" + ], + [ + "MOVPRFX", + "FRECPX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrecpx[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRECPX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrecpx[_f64]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRECPX" + ], + [ + "MOVPRFX", + "FRECPX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrecpx[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRECPX" + ], + [ + "MOVPRFX", + "FRECPX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrecpx[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRECPX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svreinterpret[_b]", + "arguments": [ + "svcount_t count" + ], + "return_type": { + "value": "svbool_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svreinterpret[_c]", + "arguments": [ + "svbool_t pg" + ], + "return_type": { + "value": "svcount_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f16[_f16]", + "arguments": [ + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f16[_f32]", + "arguments": [ + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f16[_f64]", + "arguments": [ + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f16[_s16]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f16[_s32]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f16[_s64]", + "arguments": [ + "svint64_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f16[_s8]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f16[_u16]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f16[_u32]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f16[_u64]", + "arguments": [ + "svuint64_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f16[_u8]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f32[_f16]", + "arguments": [ + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f32[_f32]", + "arguments": [ + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f32[_f64]", + "arguments": [ + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f32[_s16]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f32[_s32]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f32[_s64]", + "arguments": [ + "svint64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f32[_s8]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f32[_u16]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f32[_u32]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f32[_u64]", + "arguments": [ + "svuint64_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f32[_u8]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f64[_f16]", + "arguments": [ + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f64[_f32]", + "arguments": [ + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f64[_f64]", + "arguments": [ + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f64[_s16]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f64[_s32]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f64[_s64]", + "arguments": [ + "svint64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f64[_s8]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f64[_u16]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f64[_u32]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f64[_u64]", + "arguments": [ + "svuint64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_f64[_u8]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s16[_f16]", + "arguments": [ + "svfloat16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s16[_f32]", + "arguments": [ + "svfloat32_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s16[_f64]", + "arguments": [ + "svfloat64_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s16[_s16]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s16[_s32]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s16[_s64]", + "arguments": [ + "svint64_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s16[_s8]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s16[_u16]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s16[_u32]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s16[_u64]", + "arguments": [ + "svuint64_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s16[_u8]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s32[_f16]", + "arguments": [ + "svfloat16_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s32[_f32]", + "arguments": [ + "svfloat32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s32[_f64]", + "arguments": [ + "svfloat64_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s32[_s16]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s32[_s32]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s32[_s64]", + "arguments": [ + "svint64_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s32[_s8]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s32[_u16]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s32[_u32]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s32[_u64]", + "arguments": [ + "svuint64_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s32[_u8]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s64[_f16]", + "arguments": [ + "svfloat16_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s64[_f32]", + "arguments": [ + "svfloat32_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s64[_f64]", + "arguments": [ + "svfloat64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s64[_s16]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s64[_s32]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s64[_s64]", + "arguments": [ + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s64[_s8]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s64[_u16]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s64[_u32]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s64[_u64]", + "arguments": [ + "svuint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s64[_u8]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s8[_f16]", + "arguments": [ + "svfloat16_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s8[_f32]", + "arguments": [ + "svfloat32_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s8[_f64]", + "arguments": [ + "svfloat64_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s8[_s16]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s8[_s32]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s8[_s64]", + "arguments": [ + "svint64_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s8[_s8]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s8[_u16]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s8[_u32]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s8[_u64]", + "arguments": [ + "svuint64_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_s8[_u8]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u16[_f16]", + "arguments": [ + "svfloat16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u16[_f32]", + "arguments": [ + "svfloat32_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u16[_f64]", + "arguments": [ + "svfloat64_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u16[_s16]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u16[_s32]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u16[_s64]", + "arguments": [ + "svint64_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u16[_s8]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u16[_u16]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u16[_u32]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u16[_u64]", + "arguments": [ + "svuint64_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u16[_u8]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u32[_f16]", + "arguments": [ + "svfloat16_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u32[_f32]", + "arguments": [ + "svfloat32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u32[_f64]", + "arguments": [ + "svfloat64_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u32[_s16]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u32[_s32]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u32[_s64]", + "arguments": [ + "svint64_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u32[_s8]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u32[_u16]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u32[_u32]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u32[_u64]", + "arguments": [ + "svuint64_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u32[_u8]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u64[_f16]", + "arguments": [ + "svfloat16_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u64[_f32]", + "arguments": [ + "svfloat32_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u64[_f64]", + "arguments": [ + "svfloat64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u64[_s16]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u64[_s32]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u64[_s64]", + "arguments": [ + "svint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u64[_s8]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u64[_u16]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u64[_u32]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u64[_u64]", + "arguments": [ + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u64[_u8]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u8[_f16]", + "arguments": [ + "svfloat16_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u8[_f32]", + "arguments": [ + "svfloat32_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u8[_f64]", + "arguments": [ + "svfloat64_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u8[_s16]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u8[_s32]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u8[_s64]", + "arguments": [ + "svint64_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u8[_s8]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u8[_u16]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u8[_u32]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u8[_u64]", + "arguments": [ + "svuint64_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svreinterpret_u8[_u8]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrev[_f16]", + "arguments": [ + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrev[_f32]", + "arguments": [ + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrev[_f64]", + "arguments": [ + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrev[_s16]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrev[_s32]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrev[_s64]", + "arguments": [ + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrev[_s8]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrev[_u16]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrev[_u32]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrev[_u64]", + "arguments": [ + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrev[_u8]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrev_b16", + "arguments": [ + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Pop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrev_b32", + "arguments": [ + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Pop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrev_b64", + "arguments": [ + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Pop.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrev_b8", + "arguments": [ + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Pop.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REV" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_s16]_m", + "arguments": [ + "svint16_t inactive", + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVB" + ], + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVB" + ], + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_s32]_m", + "arguments": [ + "svint32_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVB" + ], + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVB" + ], + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_s64]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVB" + ], + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVB" + ], + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_u16]_m", + "arguments": [ + "svuint16_t inactive", + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVB" + ], + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVB" + ], + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_u32]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVB" + ], + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVB" + ], + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_u64]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVB" + ], + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVB" + ], + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevb[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "REVB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_f16]_m", + "arguments": [ + "svfloat16_t zd", + "svbool_t pg", + "svfloat16_t zn" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zd": { + "register": "Zreg1.Q" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t zn" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t zn" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOV", + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_f32]_m", + "arguments": [ + "svfloat32_t zd", + "svbool_t pg", + "svfloat32_t zn" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zd": { + "register": "Zreg1.Q" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t zn" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t zn" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOV", + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_f64]_m", + "arguments": [ + "svfloat64_t zd", + "svbool_t pg", + "svfloat64_t zn" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zd": { + "register": "Zreg1.Q" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t zn" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t zn" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOV", + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_s16]_m", + "arguments": [ + "svint16_t zd", + "svbool_t pg", + "svint16_t zn" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zd": { + "register": "Zreg1.Q" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t zn" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOV", + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t zn" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_s32]_m", + "arguments": [ + "svint32_t zd", + "svbool_t pg", + "svint32_t zn" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zd": { + "register": "Zreg1.Q" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t zn" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOV", + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t zn" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_s64]_m", + "arguments": [ + "svint64_t zd", + "svbool_t pg", + "svint64_t zn" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zd": { + "register": "Zreg1.Q" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t zn" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t zn" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOV", + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_s8]_m", + "arguments": [ + "svint8_t zd", + "svbool_t pg", + "svint8_t zn" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zd": { + "register": "Zreg1.Q" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t zn" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOV", + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t zn" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_u16]_m", + "arguments": [ + "svuint16_t zd", + "svbool_t pg", + "svuint16_t zn" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zd": { + "register": "Zreg1.Q" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t zn" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOV", + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t zn" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_u32]_m", + "arguments": [ + "svuint32_t zd", + "svbool_t pg", + "svuint32_t zn" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zd": { + "register": "Zreg1.Q" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t zn" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOV", + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t zn" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_u64]_m", + "arguments": [ + "svuint64_t zd", + "svbool_t pg", + "svuint64_t zn" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zd": { + "register": "Zreg1.Q" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t zn" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t zn" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOV", + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_u8]_m", + "arguments": [ + "svuint8_t zd", + "svbool_t pg", + "svuint8_t zn" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zd": { + "register": "Zreg1.Q" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t zn" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOV", + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrevd[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t zn" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "pg": { + "register": "Preg1" + }, + "zn": { + "register": "Zreg2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevh[_s32]_m", + "arguments": [ + "svint32_t inactive", + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVH" + ], + [ + "MOVPRFX", + "REVH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevh[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVH" + ], + [ + "MOVPRFX", + "REVH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevh[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "REVH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevh[_s64]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVH" + ], + [ + "MOVPRFX", + "REVH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevh[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVH" + ], + [ + "MOVPRFX", + "REVH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevh[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "REVH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevh[_u32]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVH" + ], + [ + "MOVPRFX", + "REVH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevh[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVH" + ], + [ + "MOVPRFX", + "REVH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevh[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "REVH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevh[_u64]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVH" + ], + [ + "MOVPRFX", + "REVH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevh[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVH" + ], + [ + "MOVPRFX", + "REVH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevh[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "REVH" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevw[_s64]_m", + "arguments": [ + "svint64_t inactive", + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVW" + ], + [ + "MOVPRFX", + "REVW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevw[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVW" + ], + [ + "MOVPRFX", + "REVW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevw[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "REVW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevw[_u64]_m", + "arguments": [ + "svuint64_t inactive", + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVW" + ], + [ + "MOVPRFX", + "REVW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevw[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "REVW" + ], + [ + "MOVPRFX", + "REVW" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrevw[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "REVW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRHADD" + ], + [ + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRHADD" + ], + [ + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRHADD" + ], + [ + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRHADD" + ], + [ + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URHADD" + ], + [ + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URHADD" + ], + [ + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URHADD" + ], + [ + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URHADD" + ], + [ + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRHADD" + ], + [ + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRHADD" + ], + [ + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRHADD" + ], + [ + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRHADD" + ], + [ + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SRHADD" + ], + [ + "MOVPRFX", + "SRHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URHADD" + ], + [ + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URHADD" + ], + [ + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URHADD" + ], + [ + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URHADD" + ], + [ + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrhadd[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URHADD" + ], + [ + "MOVPRFX", + "URHADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinta[_f16]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTA" + ], + [ + "MOVPRFX", + "FRINTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinta[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTA" + ], + [ + "MOVPRFX", + "FRINTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinta[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinta[_f32]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTA" + ], + [ + "MOVPRFX", + "FRINTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinta[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTA" + ], + [ + "MOVPRFX", + "FRINTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinta[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinta[_f64]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTA" + ], + [ + "MOVPRFX", + "FRINTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinta[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTA" + ], + [ + "MOVPRFX", + "FRINTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinta[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinti[_f16]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTI" + ], + [ + "MOVPRFX", + "FRINTI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinti[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTI" + ], + [ + "MOVPRFX", + "FRINTI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinti[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinti[_f32]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTI" + ], + [ + "MOVPRFX", + "FRINTI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinti[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTI" + ], + [ + "MOVPRFX", + "FRINTI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinti[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinti[_f64]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTI" + ], + [ + "MOVPRFX", + "FRINTI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinti[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTI" + ], + [ + "MOVPRFX", + "FRINTI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrinti[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintm[_f16]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTM" + ], + [ + "MOVPRFX", + "FRINTM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintm[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTM" + ], + [ + "MOVPRFX", + "FRINTM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintm[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintm[_f32]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTM" + ], + [ + "MOVPRFX", + "FRINTM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintm[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTM" + ], + [ + "MOVPRFX", + "FRINTM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintm[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintm[_f64]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTM" + ], + [ + "MOVPRFX", + "FRINTM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintm[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTM" + ], + [ + "MOVPRFX", + "FRINTM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintm[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTM" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintn[_f16]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTN" + ], + [ + "MOVPRFX", + "FRINTN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintn[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTN" + ], + [ + "MOVPRFX", + "FRINTN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintn[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintn[_f32]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTN" + ], + [ + "MOVPRFX", + "FRINTN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintn[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTN" + ], + [ + "MOVPRFX", + "FRINTN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintn[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintn[_f64]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTN" + ], + [ + "MOVPRFX", + "FRINTN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintn[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTN" + ], + [ + "MOVPRFX", + "FRINTN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintn[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTN" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintp[_f16]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTP" + ], + [ + "MOVPRFX", + "FRINTP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintp[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTP" + ], + [ + "MOVPRFX", + "FRINTP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintp[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintp[_f32]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTP" + ], + [ + "MOVPRFX", + "FRINTP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintp[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTP" + ], + [ + "MOVPRFX", + "FRINTP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintp[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintp[_f64]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTP" + ], + [ + "MOVPRFX", + "FRINTP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintp[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTP" + ], + [ + "MOVPRFX", + "FRINTP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintp[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTP" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintx[_f16]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTX" + ], + [ + "MOVPRFX", + "FRINTX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintx[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTX" + ], + [ + "MOVPRFX", + "FRINTX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintx[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintx[_f32]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTX" + ], + [ + "MOVPRFX", + "FRINTX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintx[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTX" + ], + [ + "MOVPRFX", + "FRINTX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintx[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintx[_f64]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTX" + ], + [ + "MOVPRFX", + "FRINTX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintx[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTX" + ], + [ + "MOVPRFX", + "FRINTX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintx[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintz[_f16]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTZ" + ], + [ + "MOVPRFX", + "FRINTZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintz[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTZ" + ], + [ + "MOVPRFX", + "FRINTZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintz[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintz[_f32]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTZ" + ], + [ + "MOVPRFX", + "FRINTZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintz[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTZ" + ], + [ + "MOVPRFX", + "FRINTZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintz[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintz[_f64]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTZ" + ], + [ + "MOVPRFX", + "FRINTZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintz[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTZ" + ], + [ + "MOVPRFX", + "FRINTZ" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrintz[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FRINTZ" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "SRSHR" + ], + [ + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "SRSHR" + ], + [ + "SRSHL" + ], + [ + "SRSHLR" + ], + [ + "MOVPRFX", + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "SRSHR" + ], + [ + "MOVPRFX", + "SRSHL" + ], + [ + "MOVPRFX", + "SRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "SRSHR" + ], + [ + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "SRSHR" + ], + [ + "SRSHL" + ], + [ + "SRSHLR" + ], + [ + "MOVPRFX", + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "SRSHR" + ], + [ + "MOVPRFX", + "SRSHL" + ], + [ + "MOVPRFX", + "SRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "SRSHR" + ], + [ + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "SRSHR" + ], + [ + "SRSHL" + ], + [ + "SRSHLR" + ], + [ + "MOVPRFX", + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "SRSHR" + ], + [ + "MOVPRFX", + "SRSHL" + ], + [ + "MOVPRFX", + "SRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "SRSHR" + ], + [ + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "SRSHR" + ], + [ + "SRSHL" + ], + [ + "SRSHLR" + ], + [ + "MOVPRFX", + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "SRSHR" + ], + [ + "MOVPRFX", + "SRSHL" + ], + [ + "MOVPRFX", + "SRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "URSHR" + ], + [ + "URSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "URSHR" + ], + [ + "URSHL" + ], + [ + "URSHLR" + ], + [ + "MOVPRFX", + "URSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "URSHR" + ], + [ + "MOVPRFX", + "URSHL" + ], + [ + "MOVPRFX", + "URSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "URSHR" + ], + [ + "URSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "URSHR" + ], + [ + "URSHL" + ], + [ + "URSHLR" + ], + [ + "MOVPRFX", + "URSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "URSHR" + ], + [ + "MOVPRFX", + "URSHL" + ], + [ + "MOVPRFX", + "URSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "URSHR" + ], + [ + "URSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "URSHR" + ], + [ + "URSHL" + ], + [ + "URSHLR" + ], + [ + "MOVPRFX", + "URSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "URSHR" + ], + [ + "MOVPRFX", + "URSHL" + ], + [ + "MOVPRFX", + "URSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "URSHR" + ], + [ + "URSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LSL" + ], + [ + "URSHR" + ], + [ + "URSHL" + ], + [ + "URSHLR" + ], + [ + "MOVPRFX", + "URSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "LSL" + ], + [ + "MOVPRFX", + "URSHR" + ], + [ + "MOVPRFX", + "URSHL" + ], + [ + "MOVPRFX", + "URSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSHL" + ], + [ + "MOVPRFX", + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSHL" + ], + [ + "SRSHLR" + ], + [ + "MOVPRFX", + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SRSHL" + ], + [ + "MOVPRFX", + "SRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSHL" + ], + [ + "MOVPRFX", + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSHL" + ], + [ + "SRSHLR" + ], + [ + "MOVPRFX", + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SRSHL" + ], + [ + "MOVPRFX", + "SRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSHL" + ], + [ + "MOVPRFX", + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSHL" + ], + [ + "SRSHLR" + ], + [ + "MOVPRFX", + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SRSHL" + ], + [ + "MOVPRFX", + "SRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSHL" + ], + [ + "MOVPRFX", + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSHL" + ], + [ + "SRSHLR" + ], + [ + "MOVPRFX", + "SRSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SRSHL" + ], + [ + "MOVPRFX", + "SRSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSHL" + ], + [ + "MOVPRFX", + "URSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSHL" + ], + [ + "URSHLR" + ], + [ + "MOVPRFX", + "URSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URSHL" + ], + [ + "MOVPRFX", + "URSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSHL" + ], + [ + "MOVPRFX", + "URSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSHL" + ], + [ + "URSHLR" + ], + [ + "MOVPRFX", + "URSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URSHL" + ], + [ + "MOVPRFX", + "URSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSHL" + ], + [ + "MOVPRFX", + "URSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSHL" + ], + [ + "URSHLR" + ], + [ + "MOVPRFX", + "URSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URSHL" + ], + [ + "MOVPRFX", + "URSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSHL" + ], + [ + "MOVPRFX", + "URSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSHL" + ], + [ + "URSHLR" + ], + [ + "MOVPRFX", + "URSHL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshl[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URSHL" + ], + [ + "MOVPRFX", + "URSHLR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSHR" + ], + [ + "MOVPRFX", + "SRSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSHR" + ], + [ + "MOVPRFX", + "SRSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SRSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSHR" + ], + [ + "MOVPRFX", + "SRSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSHR" + ], + [ + "MOVPRFX", + "SRSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SRSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSHR" + ], + [ + "MOVPRFX", + "SRSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSHR" + ], + [ + "MOVPRFX", + "SRSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Zop1.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SRSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSHR" + ], + [ + "MOVPRFX", + "SRSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSHR" + ], + [ + "MOVPRFX", + "SRSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SRSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSHR" + ], + [ + "MOVPRFX", + "URSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSHR" + ], + [ + "MOVPRFX", + "URSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSHR" + ], + [ + "MOVPRFX", + "URSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSHR" + ], + [ + "MOVPRFX", + "URSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSHR" + ], + [ + "MOVPRFX", + "URSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSHR" + ], + [ + "MOVPRFX", + "URSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Zop1.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSHR" + ], + [ + "MOVPRFX", + "URSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSHR" + ], + [ + "MOVPRFX", + "URSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshr[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URSHR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshrnb[_n_s16]", + "arguments": [ + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshrnb[_n_s32]", + "arguments": [ + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshrnb[_n_s64]", + "arguments": [ + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshrnb[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshrnb[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshrnb[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshrnt[_n_s16]", + "arguments": [ + "svint8_t even", + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshrnt[_n_s32]", + "arguments": [ + "svint16_t even", + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshrnt[_n_s64]", + "arguments": [ + "svint32_t even", + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshrnt[_n_u16]", + "arguments": [ + "svuint8_t even", + "svuint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshrnt[_n_u32]", + "arguments": [ + "svuint16_t even", + "svuint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrshrnt[_n_u64]", + "arguments": [ + "svuint32_t even", + "svuint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrsqrte[_f16]", + "arguments": [ + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRSQRTE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrsqrte[_f32]", + "arguments": [ + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRSQRTE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrsqrte[_f64]", + "arguments": [ + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRSQRTE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsqrte[_u32]_m", + "arguments": [ + "svuint32_t inactive", + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSQRTE" + ], + [ + "MOVPRFX", + "URSQRTE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsqrte[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSQRTE" + ], + [ + "MOVPRFX", + "URSQRTE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsqrte[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "URSQRTE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrsqrts[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRSQRTS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrsqrts[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRSQRTS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svrsqrts[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRSQRTS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsra[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSRA" + ], + [ + "MOVPRFX", + "SRSRA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsra[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSRA" + ], + [ + "MOVPRFX", + "SRSRA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsra[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSRA" + ], + [ + "MOVPRFX", + "SRSRA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsra[_n_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRSRA" + ], + [ + "MOVPRFX", + "SRSRA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsra[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSRA" + ], + [ + "MOVPRFX", + "URSRA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsra[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSRA" + ], + [ + "MOVPRFX", + "URSRA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsra[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSRA" + ], + [ + "MOVPRFX", + "URSRA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsra[_n_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "URSRA" + ], + [ + "MOVPRFX", + "URSRA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnb[_n_s16]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnb[_n_s32]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnb[_n_s64]", + "arguments": [ + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnb[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnb[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnb[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnb[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnb[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnb[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnb[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnb[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnb[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_n_s16]", + "arguments": [ + "svint8_t even", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_n_s32]", + "arguments": [ + "svint16_t even", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_n_s64]", + "arguments": [ + "svint32_t even", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_n_u16]", + "arguments": [ + "svuint8_t even", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_n_u32]", + "arguments": [ + "svuint16_t even", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_n_u64]", + "arguments": [ + "svuint32_t even", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_s16]", + "arguments": [ + "svint8_t even", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_s32]", + "arguments": [ + "svint16_t even", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_s64]", + "arguments": [ + "svint32_t even", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_u16]", + "arguments": [ + "svuint8_t even", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_u32]", + "arguments": [ + "svuint16_t even", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svrsubhnt[_u64]", + "arguments": [ + "svuint32_t even", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RSUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsbclb[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SBCLB" + ], + [ + "MOVPRFX", + "SBCLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsbclb[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SBCLB" + ], + [ + "MOVPRFX", + "SBCLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsbclb[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SBCLB" + ], + [ + "MOVPRFX", + "SBCLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsbclb[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SBCLB" + ], + [ + "MOVPRFX", + "SBCLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsbclt[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SBCLT" + ], + [ + "MOVPRFX", + "SBCLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsbclt[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SBCLT" + ], + [ + "MOVPRFX", + "SBCLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsbclt[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "svuint32_t op3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SBCLT" + ], + [ + "MOVPRFX", + "SBCLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsbclt[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "svuint64_t op3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SBCLT" + ], + [ + "MOVPRFX", + "SBCLT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svscale[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ], + [ + "MOVPRFX", "FSCALE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vscaleq_f16", + "SIMD_ISA": "SVE", + "name": "svscale[_f16]_x", "arguments": [ - "float16x8_t a", - "int16x8_t b" + "svbool_t pg", + "svfloat16_t op1", + "svint16_t op2" ], "return_type": { - "value": "float16x8_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.8H" + "op1": { + "register": "Zop1.H|Ztied1.H" }, - "b": { - "register": "Vm.8H" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -274,25 +165327,33 @@ "instructions": [ [ "FSCALE" + ], + [ + "MOVPRFX", + "FSCALE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vscale_f32", + "SIMD_ISA": "SVE", + "name": "svscale[_f16]_z", "arguments": [ - "float32x2_t a", - "int32x2_t b" + "svbool_t pg", + "svfloat16_t op1", + "svint16_t op2" ], "return_type": { - "value": "float32x2_t" + "value": "svfloat16_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2S" + "op1": { + "register": "Zop1.H" }, - "b": { - "register": "Vm.2S" + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" } }, "Architectures": [ @@ -300,26 +165361,31 @@ ], "instructions": [ [ + "MOVPRFX", "FSCALE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vscaleq_f32", + "SIMD_ISA": "SVE", + "name": "svscale[_f32]_m", "arguments": [ - "float32x4_t a", - "int32x4_t b" + "svbool_t pg", + "svfloat32_t op1", + "svint32_t op2" ], "return_type": { - "value": "float32x4_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.4S" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.4S" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -328,25 +165394,33 @@ "instructions": [ [ "FSCALE" + ], + [ + "MOVPRFX", + "FSCALE" ] ] }, { - "SIMD_ISA": "Neon", - "name": "vscaleq_f64", + "SIMD_ISA": "SVE", + "name": "svscale[_f32]_x", "arguments": [ - "float64x2_t a", - "int64x2_t b" + "svbool_t pg", + "svfloat32_t op1", + "svint32_t op2" ], "return_type": { - "value": "float64x2_t" + "value": "svfloat32_t" }, "Arguments_Preparation": { - "a": { - "register": "Vn.2D" + "op1": { + "register": "Zop1.S|Ztied1.S" }, - "b": { - "register": "Vm.2D" + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" } }, "Architectures": [ @@ -355,6 +165429,37649 @@ "instructions": [ [ "FSCALE" + ], + [ + "MOVPRFX", + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svscale[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svscale[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ], + [ + "MOVPRFX", + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svscale[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ], + [ + "MOVPRFX", + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svscale[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svscale[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ], + [ + "MOVPRFX", + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svscale[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ], + [ + "MOVPRFX", + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svscale[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svscale[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ], + [ + "MOVPRFX", + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svscale[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ], + [ + "MOVPRFX", + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svscale[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svscale[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ], + [ + "MOVPRFX", + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svscale[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ], + [ + "MOVPRFX", + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svscale[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsel[_b]", + "arguments": [ + "svbool_t pg", + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SEL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsel[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SEL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsel[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SEL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsel[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SEL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsel[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SEL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsel[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SEL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsel[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SEL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsel[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SEL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsel[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SEL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsel[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SEL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsel[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SEL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsel[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SEL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svset2[_b]", + "arguments": [ + "svboolx2_t tuple", + "uint64_t imm_index", + "svbool_t x" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset2[_f16]", + "arguments": [ + "svfloat16x2_t tuple", + "uint64_t imm_index", + "svfloat16_t x" + ], + "return_type": { + "value": "svfloat16x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset2[_f32]", + "arguments": [ + "svfloat32x2_t tuple", + "uint64_t imm_index", + "svfloat32_t x" + ], + "return_type": { + "value": "svfloat32x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset2[_f64]", + "arguments": [ + "svfloat64x2_t tuple", + "uint64_t imm_index", + "svfloat64_t x" + ], + "return_type": { + "value": "svfloat64x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset2[_s16]", + "arguments": [ + "svint16x2_t tuple", + "uint64_t imm_index", + "svint16_t x" + ], + "return_type": { + "value": "svint16x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset2[_s32]", + "arguments": [ + "svint32x2_t tuple", + "uint64_t imm_index", + "svint32_t x" + ], + "return_type": { + "value": "svint32x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset2[_s64]", + "arguments": [ + "svint64x2_t tuple", + "uint64_t imm_index", + "svint64_t x" + ], + "return_type": { + "value": "svint64x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset2[_s8]", + "arguments": [ + "svint8x2_t tuple", + "uint64_t imm_index", + "svint8_t x" + ], + "return_type": { + "value": "svint8x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset2[_u16]", + "arguments": [ + "svuint16x2_t tuple", + "uint64_t imm_index", + "svuint16_t x" + ], + "return_type": { + "value": "svuint16x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset2[_u32]", + "arguments": [ + "svuint32x2_t tuple", + "uint64_t imm_index", + "svuint32_t x" + ], + "return_type": { + "value": "svuint32x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset2[_u64]", + "arguments": [ + "svuint64x2_t tuple", + "uint64_t imm_index", + "svuint64_t x" + ], + "return_type": { + "value": "svuint64x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset2[_u8]", + "arguments": [ + "svuint8x2_t tuple", + "uint64_t imm_index", + "svuint8_t x" + ], + "return_type": { + "value": "svuint8x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset3[_f16]", + "arguments": [ + "svfloat16x3_t tuple", + "uint64_t imm_index", + "svfloat16_t x" + ], + "return_type": { + "value": "svfloat16x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset3[_f32]", + "arguments": [ + "svfloat32x3_t tuple", + "uint64_t imm_index", + "svfloat32_t x" + ], + "return_type": { + "value": "svfloat32x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset3[_f64]", + "arguments": [ + "svfloat64x3_t tuple", + "uint64_t imm_index", + "svfloat64_t x" + ], + "return_type": { + "value": "svfloat64x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset3[_s16]", + "arguments": [ + "svint16x3_t tuple", + "uint64_t imm_index", + "svint16_t x" + ], + "return_type": { + "value": "svint16x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset3[_s32]", + "arguments": [ + "svint32x3_t tuple", + "uint64_t imm_index", + "svint32_t x" + ], + "return_type": { + "value": "svint32x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset3[_s64]", + "arguments": [ + "svint64x3_t tuple", + "uint64_t imm_index", + "svint64_t x" + ], + "return_type": { + "value": "svint64x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset3[_s8]", + "arguments": [ + "svint8x3_t tuple", + "uint64_t imm_index", + "svint8_t x" + ], + "return_type": { + "value": "svint8x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset3[_u16]", + "arguments": [ + "svuint16x3_t tuple", + "uint64_t imm_index", + "svuint16_t x" + ], + "return_type": { + "value": "svuint16x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset3[_u32]", + "arguments": [ + "svuint32x3_t tuple", + "uint64_t imm_index", + "svuint32_t x" + ], + "return_type": { + "value": "svuint32x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset3[_u64]", + "arguments": [ + "svuint64x3_t tuple", + "uint64_t imm_index", + "svuint64_t x" + ], + "return_type": { + "value": "svuint64x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset3[_u8]", + "arguments": [ + "svuint8x3_t tuple", + "uint64_t imm_index", + "svuint8_t x" + ], + "return_type": { + "value": "svuint8x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svset4[_b]", + "arguments": [ + "svboolx4_t tuple", + "uint64_t imm_index", + "svbool_t x" + ], + "return_type": { + "value": "svboolx4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset4[_f16]", + "arguments": [ + "svfloat16x4_t tuple", + "uint64_t imm_index", + "svfloat16_t x" + ], + "return_type": { + "value": "svfloat16x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset4[_f32]", + "arguments": [ + "svfloat32x4_t tuple", + "uint64_t imm_index", + "svfloat32_t x" + ], + "return_type": { + "value": "svfloat32x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset4[_f64]", + "arguments": [ + "svfloat64x4_t tuple", + "uint64_t imm_index", + "svfloat64_t x" + ], + "return_type": { + "value": "svfloat64x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset4[_s16]", + "arguments": [ + "svint16x4_t tuple", + "uint64_t imm_index", + "svint16_t x" + ], + "return_type": { + "value": "svint16x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset4[_s32]", + "arguments": [ + "svint32x4_t tuple", + "uint64_t imm_index", + "svint32_t x" + ], + "return_type": { + "value": "svint32x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset4[_s64]", + "arguments": [ + "svint64x4_t tuple", + "uint64_t imm_index", + "svint64_t x" + ], + "return_type": { + "value": "svint64x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset4[_s8]", + "arguments": [ + "svint8x4_t tuple", + "uint64_t imm_index", + "svint8_t x" + ], + "return_type": { + "value": "svint8x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset4[_u16]", + "arguments": [ + "svuint16x4_t tuple", + "uint64_t imm_index", + "svuint16_t x" + ], + "return_type": { + "value": "svuint16x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset4[_u32]", + "arguments": [ + "svuint32x4_t tuple", + "uint64_t imm_index", + "svuint32_t x" + ], + "return_type": { + "value": "svuint32x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset4[_u64]", + "arguments": [ + "svuint64x4_t tuple", + "uint64_t imm_index", + "svuint64_t x" + ], + "return_type": { + "value": "svuint64x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svset4[_u8]", + "arguments": [ + "svuint8x4_t tuple", + "uint64_t imm_index", + "svuint8_t x" + ], + "return_type": { + "value": "svuint8x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsetffr", + "arguments": [], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": {}, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SETFFR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshllb[_n_s16]", + "arguments": [ + "svint8_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSHLLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshllb[_n_s32]", + "arguments": [ + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 15 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSHLLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshllb[_n_s64]", + "arguments": [ + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 31 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSHLLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshllb[_n_u16]", + "arguments": [ + "svuint8_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USHLLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshllb[_n_u32]", + "arguments": [ + "svuint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 15 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USHLLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshllb[_n_u64]", + "arguments": [ + "svuint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 31 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USHLLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshllt[_n_s16]", + "arguments": [ + "svint8_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSHLLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshllt[_n_s32]", + "arguments": [ + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 15 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSHLLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshllt[_n_s64]", + "arguments": [ + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 31 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSHLLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshllt[_n_u16]", + "arguments": [ + "svuint8_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USHLLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshllt[_n_u32]", + "arguments": [ + "svuint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 15 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USHLLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshllt[_n_u64]", + "arguments": [ + "svuint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 0, + "maximum": 31 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USHLLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshrnb[_n_s16]", + "arguments": [ + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshrnb[_n_s32]", + "arguments": [ + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshrnb[_n_s64]", + "arguments": [ + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshrnb[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshrnb[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshrnb[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHRNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshrnt[_n_s16]", + "arguments": [ + "svint8_t even", + "svint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshrnt[_n_s32]", + "arguments": [ + "svint16_t even", + "svint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshrnt[_n_s64]", + "arguments": [ + "svint32_t even", + "svint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshrnt[_n_u16]", + "arguments": [ + "svuint8_t even", + "svuint16_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "imm2": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshrnt[_n_u32]", + "arguments": [ + "svuint16_t even", + "svuint32_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "imm2": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svshrnt[_n_u64]", + "arguments": [ + "svuint32_t even", + "svuint64_t op1", + "uint64_t imm2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "imm2": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SHRNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsli[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 15 + }, + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SLI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsli[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 31 + }, + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SLI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsli[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 63 + }, + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SLI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsli[_n_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SLI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsli[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 15 + }, + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SLI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsli[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 31 + }, + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SLI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsli[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 63 + }, + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SLI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsli[_n_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SLI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsm4e[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SM4E" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsm4ekey[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SM4EKEY" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsplice[_f16]", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SPLICE" + ], + [ + "MOVPRFX", + "SPLICE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsplice[_f32]", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SPLICE" + ], + [ + "MOVPRFX", + "SPLICE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsplice[_f64]", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SPLICE" + ], + [ + "MOVPRFX", + "SPLICE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsplice[_s16]", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SPLICE" + ], + [ + "MOVPRFX", + "SPLICE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsplice[_s32]", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SPLICE" + ], + [ + "MOVPRFX", + "SPLICE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsplice[_s64]", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SPLICE" + ], + [ + "MOVPRFX", + "SPLICE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsplice[_s8]", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SPLICE" + ], + [ + "MOVPRFX", + "SPLICE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsplice[_u16]", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SPLICE" + ], + [ + "MOVPRFX", + "SPLICE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsplice[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SPLICE" + ], + [ + "MOVPRFX", + "SPLICE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsplice[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SPLICE" + ], + [ + "MOVPRFX", + "SPLICE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsplice[_u8]", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SPLICE" + ], + [ + "MOVPRFX", + "SPLICE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USQADD" + ], + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USQADD" + ], + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USQADD" + ], + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USQADD" + ], + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UQADD" + ], + [ + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USQADD" + ], + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USQADD" + ], + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USQADD" + ], + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USQADD" + ], + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USQADD" + ], + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USQADD" + ], + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USQADD" + ], + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USQADD" + ], + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsqadd[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "USQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsqrt[_f16]_m", + "arguments": [ + "svfloat16_t inactive", + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.H|Ztied.H" + }, + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSQRT" + ], + [ + "MOVPRFX", + "FSQRT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsqrt[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H|Ztied.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSQRT" + ], + [ + "MOVPRFX", + "FSQRT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsqrt[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSQRT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsqrt[_f32]_m", + "arguments": [ + "svfloat32_t inactive", + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.S|Ztied.S" + }, + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSQRT" + ], + [ + "MOVPRFX", + "FSQRT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsqrt[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S|Ztied.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSQRT" + ], + [ + "MOVPRFX", + "FSQRT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsqrt[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSQRT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsqrt[_f64]_m", + "arguments": [ + "svfloat64_t inactive", + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "inactive": { + "register": "Zinactive.D|Ztied.D" + }, + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSQRT" + ], + [ + "MOVPRFX", + "FSQRT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsqrt[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D|Ztied.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSQRT" + ], + [ + "MOVPRFX", + "FSQRT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsqrt[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSQRT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsra[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSRA" + ], + [ + "MOVPRFX", + "SSRA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsra[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSRA" + ], + [ + "MOVPRFX", + "SSRA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsra[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSRA" + ], + [ + "MOVPRFX", + "SSRA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsra[_n_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSRA" + ], + [ + "MOVPRFX", + "SSRA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsra[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USRA" + ], + [ + "MOVPRFX", + "USRA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsra[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USRA" + ], + [ + "MOVPRFX", + "USRA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsra[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USRA" + ], + [ + "MOVPRFX", + "USRA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsra[_n_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USRA" + ], + [ + "MOVPRFX", + "USRA" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsri[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsri[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsri[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsri[_n_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsri[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsri[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsri[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsri[_n_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SRI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1[_f16]", + "arguments": [ + "svbool_t pg", + "float16_t *base", + "svfloat16_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_f16_x2]", + "arguments": [ + "svcount_t png", + "float16_t * rn", + "svfloat16x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H, Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_f16_x4]", + "arguments": [ + "svcount_t png", + "float16_t * rn", + "svfloat16x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H - Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1[_f32]", + "arguments": [ + "svbool_t pg", + "float32_t *base", + "svfloat32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_f32_x2]", + "arguments": [ + "svcount_t png", + "float32_t * rn", + "svfloat32x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S, Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_f32_x4]", + "arguments": [ + "svcount_t png", + "float32_t * rn", + "svfloat32x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S - Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ], + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_f64_x2]", + "arguments": [ + "svcount_t png", + "float64_t * rn", + "svfloat64x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D, Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_f64_x4]", + "arguments": [ + "svcount_t png", + "float64_t * rn", + "svfloat64x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D - Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1[_s16]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svint16_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_s16_x2]", + "arguments": [ + "svcount_t png", + "int16_t * rn", + "svint16x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H, Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_s16_x4]", + "arguments": [ + "svcount_t png", + "int16_t * rn", + "svint16x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H - Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1[_s32]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_s32_x2]", + "arguments": [ + "svcount_t png", + "int32_t * rn", + "svint32x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S, Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_s32_x4]", + "arguments": [ + "svcount_t png", + "int32_t * rn", + "svint32x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S - Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ], + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_s64_x2]", + "arguments": [ + "svcount_t png", + "int64_t * rn", + "svint64x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D, Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_s64_x4]", + "arguments": [ + "svcount_t png", + "int64_t * rn", + "svint64x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D - Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1[_s8]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "svint8_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_s8_x2]", + "arguments": [ + "svcount_t png", + "int8_t * rn", + "svint8x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.B, Zreg2.B }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_s8_x4]", + "arguments": [ + "svcount_t png", + "int8_t * rn", + "svint8x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.B - Zreg2.B }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1[_u16]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svuint16_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_u16_x2]", + "arguments": [ + "svcount_t png", + "uint16_t * rn", + "svuint16x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H, Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_u16_x4]", + "arguments": [ + "svcount_t png", + "uint16_t * rn", + "svuint16x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H - Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1[_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_u32_x2]", + "arguments": [ + "svcount_t png", + "uint32_t * rn", + "svuint32x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S, Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_u32_x4]", + "arguments": [ + "svcount_t png", + "uint32_t * rn", + "svuint32x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S - Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ], + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_u64_x2]", + "arguments": [ + "svcount_t png", + "uint64_t * rn", + "svuint64x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D, Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_u64_x4]", + "arguments": [ + "svcount_t png", + "uint64_t * rn", + "svuint64x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D - Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1[_u8]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "svuint8_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_u8_x2]", + "arguments": [ + "svcount_t png", + "uint8_t * rn", + "svuint8x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.B, Zreg2.B }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1[_u8_x4]", + "arguments": [ + "svcount_t png", + "uint8_t * rn", + "svuint8x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.B - Zreg2.B }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u32base]_index[_f32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index", + "svfloat32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u32base]_index[_s32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u32base]_index[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u32base]_offset[_f32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset", + "svfloat32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u32base]_offset[_s32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u32base]_offset[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u32base_f32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "svfloat32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u32base_s32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u32base_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u64base]_index[_f64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ], + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u64base]_index[_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ], + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u64base]_index[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ], + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u64base]_offset[_f64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ], + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u64base]_offset[_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ], + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u64base]_offset[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ], + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u64base_f64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u64base_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter[_u64base_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[s32]index[_f32]", + "arguments": [ + "svbool_t pg", + "float32_t *base", + "svint32_t indices", + "svfloat32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[s32]index[_s32]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svint32_t indices", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[s32]index[_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svint32_t indices", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[s32]offset[_f32]", + "arguments": [ + "svbool_t pg", + "float32_t *base", + "svint32_t offsets", + "svfloat32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[s32]offset[_s32]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svint32_t offsets", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[s32]offset[_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svint32_t offsets", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[s64]index[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "svint64_t indices", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[s64]index[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "svint64_t indices", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[s64]index[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "svint64_t indices", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[s64]offset[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "svint64_t offsets", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[s64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "svint64_t offsets", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[s64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "svint64_t offsets", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[u32]index[_f32]", + "arguments": [ + "svbool_t pg", + "float32_t *base", + "svuint32_t indices", + "svfloat32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[u32]index[_s32]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svuint32_t indices", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[u32]index[_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svuint32_t indices", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[u32]offset[_f32]", + "arguments": [ + "svbool_t pg", + "float32_t *base", + "svuint32_t offsets", + "svfloat32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[u32]offset[_s32]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svuint32_t offsets", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[u32]offset[_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svuint32_t offsets", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[u64]index[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "svuint64_t indices", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[u64]index[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "svuint64_t indices", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[u64]index[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "svuint64_t indices", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[u64]offset[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "svuint64_t offsets", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[u64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "svuint64_t offsets", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_scatter_[u64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "svuint64_t offsets", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_vnum[_f16]", + "arguments": [ + "svbool_t pg", + "float16_t *base", + "int64_t vnum", + "svfloat16_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.H" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_f16_x2]", + "arguments": [ + "svcount_t png", + "float16_t * rn", + "int64_t vnum", + "svfloat16x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H, Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_f16_x4]", + "arguments": [ + "svcount_t png", + "float16_t * rn", + "int64_t vnum", + "svfloat16x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H - Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_vnum[_f32]", + "arguments": [ + "svbool_t pg", + "float32_t *base", + "int64_t vnum", + "svfloat32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_f32_x2]", + "arguments": [ + "svcount_t png", + "float32_t * rn", + "int64_t vnum", + "svfloat32x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S, Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_f32_x4]", + "arguments": [ + "svcount_t png", + "float32_t * rn", + "int64_t vnum", + "svfloat32x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S - Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_vnum[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "int64_t vnum", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ], + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_f64_x2]", + "arguments": [ + "svcount_t png", + "float64_t * rn", + "int64_t vnum", + "svfloat64x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D, Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_f64_x4]", + "arguments": [ + "svcount_t png", + "float64_t * rn", + "int64_t vnum", + "svfloat64x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D - Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_vnum[_s16]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "int64_t vnum", + "svint16_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.H" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_s16_x2]", + "arguments": [ + "svcount_t png", + "int16_t * rn", + "int64_t vnum", + "svint16x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H, Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_s16_x4]", + "arguments": [ + "svcount_t png", + "int16_t * rn", + "int64_t vnum", + "svint16x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H - Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_vnum[_s32]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "int64_t vnum", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_s32_x2]", + "arguments": [ + "svcount_t png", + "int32_t * rn", + "int64_t vnum", + "svint32x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S, Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_s32_x4]", + "arguments": [ + "svcount_t png", + "int32_t * rn", + "int64_t vnum", + "svint32x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S - Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_vnum[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "int64_t vnum", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ], + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_s64_x2]", + "arguments": [ + "svcount_t png", + "int64_t * rn", + "int64_t vnum", + "svint64x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D, Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_s64_x4]", + "arguments": [ + "svcount_t png", + "int64_t * rn", + "int64_t vnum", + "svint64x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D - Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_vnum[_s8]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "int64_t vnum", + "svint8_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.B" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_s8_x2]", + "arguments": [ + "svcount_t png", + "int8_t * rn", + "int64_t vnum", + "svint8x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.B, Zreg2.B }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_s8_x4]", + "arguments": [ + "svcount_t png", + "int8_t * rn", + "int64_t vnum", + "svint8x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.B - Zreg2.B }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_vnum[_u16]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "int64_t vnum", + "svuint16_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.H" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_u16_x2]", + "arguments": [ + "svcount_t png", + "uint16_t * rn", + "int64_t vnum", + "svuint16x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H, Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_u16_x4]", + "arguments": [ + "svcount_t png", + "uint16_t * rn", + "int64_t vnum", + "svuint16x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H - Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_vnum[_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "int64_t vnum", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_u32_x2]", + "arguments": [ + "svcount_t png", + "uint32_t * rn", + "int64_t vnum", + "svuint32x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S, Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_u32_x4]", + "arguments": [ + "svcount_t png", + "uint32_t * rn", + "int64_t vnum", + "svuint32x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S - Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_vnum[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "int64_t vnum", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1D" + ], + [ + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_u64_x2]", + "arguments": [ + "svcount_t png", + "uint64_t * rn", + "int64_t vnum", + "svuint64x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D, Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_u64_x4]", + "arguments": [ + "svcount_t png", + "uint64_t * rn", + "int64_t vnum", + "svuint64x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D - Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1_vnum[_u8]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "int64_t vnum", + "svuint8_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.B" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_u8_x2]", + "arguments": [ + "svcount_t png", + "uint8_t * rn", + "int64_t vnum", + "svuint8x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.B, Zreg2.B }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svst1_vnum[_u8_x4]", + "arguments": [ + "svcount_t png", + "uint8_t * rn", + "int64_t vnum", + "svuint8x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.B - Zreg2.B }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b[_s16]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "svint16_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b[_s32]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b[_s64]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b[_u16]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "svuint16_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b[_u32]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b[_u64]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_scatter[_u32base]_offset[_s32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_scatter[_u32base]_offset[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_scatter[_u32base_s32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_scatter[_u32base_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_scatter[_u64base]_offset[_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_scatter[_u64base]_offset[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_scatter[_u64base_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_scatter[_u64base_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_scatter_[s32]offset[_s32]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "svint32_t offsets", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_scatter_[s32]offset[_u32]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "svint32_t offsets", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_scatter_[s64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "svint64_t offsets", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_scatter_[s64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "svint64_t offsets", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_scatter_[u32]offset[_s32]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "svuint32_t offsets", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_scatter_[u32]offset[_u32]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "svuint32_t offsets", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_scatter_[u64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "svuint64_t offsets", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_scatter_[u64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "svuint64_t offsets", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_vnum[_s16]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "int64_t vnum", + "svint16_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.H" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_vnum[_s32]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "int64_t vnum", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_vnum[_s64]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "int64_t vnum", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_vnum[_u16]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "int64_t vnum", + "svuint16_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.H" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_vnum[_u32]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "int64_t vnum", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1b_vnum[_u64]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "int64_t vnum", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1B" + ], + [ + "ST1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h[_s32]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h[_s64]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h[_u32]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h[_u64]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter[_u32base]_index[_s32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter[_u32base]_index[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter[_u32base]_offset[_s32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter[_u32base]_offset[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter[_u32base_s32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter[_u32base_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter[_u64base]_index[_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter[_u64base]_index[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter[_u64base]_offset[_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter[_u64base]_offset[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter[_u64base_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter[_u64base_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter_[s32]index[_s32]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svint32_t indices", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter_[s32]index[_u32]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svint32_t indices", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter_[s32]offset[_s32]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svint32_t offsets", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter_[s32]offset[_u32]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svint32_t offsets", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter_[s64]index[_s64]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svint64_t indices", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter_[s64]index[_u64]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svint64_t indices", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter_[s64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svint64_t offsets", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter_[s64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svint64_t offsets", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter_[u32]index[_s32]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svuint32_t indices", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter_[u32]index[_u32]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svuint32_t indices", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "indices": { + "register": "Zindices.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter_[u32]offset[_s32]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svuint32_t offsets", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter_[u32]offset[_u32]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svuint32_t offsets", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter_[u64]index[_s64]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svuint64_t indices", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter_[u64]index[_u64]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svuint64_t indices", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter_[u64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svuint64_t offsets", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_scatter_[u64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svuint64_t offsets", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_vnum[_s32]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "int64_t vnum", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_vnum[_s64]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "int64_t vnum", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_vnum[_u32]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "int64_t vnum", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1h_vnum[_u64]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "int64_t vnum", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1H" + ], + [ + "ST1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w[_s64]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w[_u64]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w_scatter[_u64base]_index[_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w_scatter[_u64base]_index[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w_scatter[_u64base]_offset[_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w_scatter[_u64base]_offset[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w_scatter[_u64base_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w_scatter[_u64base_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w_scatter_[s64]index[_s64]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svint64_t indices", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w_scatter_[s64]index[_u64]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svint64_t indices", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w_scatter_[s64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svint64_t offsets", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w_scatter_[s64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svint64_t offsets", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w_scatter_[u64]index[_s64]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svuint64_t indices", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w_scatter_[u64]index[_u64]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svuint64_t indices", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w_scatter_[u64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svuint64_t offsets", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w_scatter_[u64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svuint64_t offsets", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w_vnum[_s64]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "int64_t vnum", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst1w_vnum[_u64]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "int64_t vnum", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1W" + ], + [ + "ST1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2[_f16]", + "arguments": [ + "svbool_t pg", + "float16_t *base", + "svfloat16x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H, Zdata1.H}" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2H" + ], + [ + "ST2H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2[_f32]", + "arguments": [ + "svbool_t pg", + "float32_t *base", + "svfloat32x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S, Zdata1.S}" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2W" + ], + [ + "ST2W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "svfloat64x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D, Zdata1.D}" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2D" + ], + [ + "ST2D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2[_s16]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svint16x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H, Zdata1.H}" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2H" + ], + [ + "ST2H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2[_s32]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svint32x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S, Zdata1.S}" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2W" + ], + [ + "ST2W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "svint64x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D, Zdata1.D}" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2D" + ], + [ + "ST2D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2[_s8]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "svint8x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.B, Zdata1.B}" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2B" + ], + [ + "ST2B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2[_u16]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svuint16x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H, Zdata1.H}" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2H" + ], + [ + "ST2H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2[_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svuint32x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S, Zdata1.S}" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2W" + ], + [ + "ST2W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "svuint64x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D, Zdata1.D}" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2D" + ], + [ + "ST2D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2[_u8]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "svuint8x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.B, Zdata1.B}" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2B" + ], + [ + "ST2B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2_vnum[_f16]", + "arguments": [ + "svbool_t pg", + "float16_t *base", + "int64_t vnum", + "svfloat16x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H, Zdata1.H}" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2H" + ], + [ + "ST2H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2_vnum[_f32]", + "arguments": [ + "svbool_t pg", + "float32_t *base", + "int64_t vnum", + "svfloat32x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S, Zdata1.S}" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2W" + ], + [ + "ST2W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2_vnum[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "int64_t vnum", + "svfloat64x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D, Zdata1.D}" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2D" + ], + [ + "ST2D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2_vnum[_s16]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "int64_t vnum", + "svint16x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H, Zdata1.H}" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2H" + ], + [ + "ST2H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2_vnum[_s32]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "int64_t vnum", + "svint32x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S, Zdata1.S}" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2W" + ], + [ + "ST2W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2_vnum[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "int64_t vnum", + "svint64x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D, Zdata1.D}" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2D" + ], + [ + "ST2D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2_vnum[_s8]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "int64_t vnum", + "svint8x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.B, Zdata1.B}" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2B" + ], + [ + "ST2B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2_vnum[_u16]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "int64_t vnum", + "svuint16x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H, Zdata1.H}" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2H" + ], + [ + "ST2H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2_vnum[_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "int64_t vnum", + "svuint32x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S, Zdata1.S}" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2W" + ], + [ + "ST2W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2_vnum[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "int64_t vnum", + "svuint64x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D, Zdata1.D}" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2D" + ], + [ + "ST2D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst2_vnum[_u8]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "int64_t vnum", + "svuint8x2_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.B, Zdata1.B}" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST2B" + ], + [ + "ST2B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3[_f16]", + "arguments": [ + "svbool_t pg", + "float16_t *base", + "svfloat16x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H - Zdata2.H}" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3H" + ], + [ + "ST3H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3[_f32]", + "arguments": [ + "svbool_t pg", + "float32_t *base", + "svfloat32x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S - Zdata2.S}" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3W" + ], + [ + "ST3W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "svfloat64x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D - Zdata2.D}" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3D" + ], + [ + "ST3D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3[_s16]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svint16x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H - Zdata2.H}" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3H" + ], + [ + "ST3H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3[_s32]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svint32x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S - Zdata2.S}" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3W" + ], + [ + "ST3W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "svint64x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D - Zdata2.D}" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3D" + ], + [ + "ST3D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3[_s8]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "svint8x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.B - Zdata2.B}" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3B" + ], + [ + "ST3B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3[_u16]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svuint16x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H - Zdata2.H}" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3H" + ], + [ + "ST3H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3[_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svuint32x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S - Zdata2.S}" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3W" + ], + [ + "ST3W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "svuint64x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D - Zdata2.D}" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3D" + ], + [ + "ST3D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3[_u8]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "svuint8x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.B - Zdata2.B}" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3B" + ], + [ + "ST3B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3_vnum[_f16]", + "arguments": [ + "svbool_t pg", + "float16_t *base", + "int64_t vnum", + "svfloat16x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H - Zdata2.H}" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3H" + ], + [ + "ST3H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3_vnum[_f32]", + "arguments": [ + "svbool_t pg", + "float32_t *base", + "int64_t vnum", + "svfloat32x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S - Zdata2.S}" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3W" + ], + [ + "ST3W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3_vnum[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "int64_t vnum", + "svfloat64x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D - Zdata2.D}" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3D" + ], + [ + "ST3D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3_vnum[_s16]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "int64_t vnum", + "svint16x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H - Zdata2.H}" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3H" + ], + [ + "ST3H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3_vnum[_s32]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "int64_t vnum", + "svint32x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S - Zdata2.S}" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3W" + ], + [ + "ST3W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3_vnum[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "int64_t vnum", + "svint64x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D - Zdata2.D}" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3D" + ], + [ + "ST3D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3_vnum[_s8]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "int64_t vnum", + "svint8x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.B - Zdata2.B}" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3B" + ], + [ + "ST3B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3_vnum[_u16]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "int64_t vnum", + "svuint16x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H - Zdata2.H}" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3H" + ], + [ + "ST3H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3_vnum[_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "int64_t vnum", + "svuint32x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S - Zdata2.S}" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3W" + ], + [ + "ST3W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3_vnum[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "int64_t vnum", + "svuint64x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D - Zdata2.D}" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3D" + ], + [ + "ST3D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst3_vnum[_u8]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "int64_t vnum", + "svuint8x3_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.B - Zdata2.B}" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST3B" + ], + [ + "ST3B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4[_f16]", + "arguments": [ + "svbool_t pg", + "float16_t *base", + "svfloat16x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H - Zdata3.H}" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4H" + ], + [ + "ST4H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4[_f32]", + "arguments": [ + "svbool_t pg", + "float32_t *base", + "svfloat32x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S - Zdata3.S}" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4W" + ], + [ + "ST4W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "svfloat64x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D - Zdata3.D}" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4D" + ], + [ + "ST4D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4[_s16]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svint16x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H - Zdata3.H}" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4H" + ], + [ + "ST4H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4[_s32]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svint32x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S - Zdata3.S}" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4W" + ], + [ + "ST4W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "svint64x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D - Zdata3.D}" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4D" + ], + [ + "ST4D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4[_s8]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "svint8x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.B - Zdata3.B}" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4B" + ], + [ + "ST4B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4[_u16]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svuint16x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H - Zdata3.H}" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4H" + ], + [ + "ST4H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4[_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svuint32x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S - Zdata3.S}" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4W" + ], + [ + "ST4W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "svuint64x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D - Zdata3.D}" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4D" + ], + [ + "ST4D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4[_u8]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "svuint8x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.B - Zdata3.B}" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4B" + ], + [ + "ST4B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4_vnum[_f16]", + "arguments": [ + "svbool_t pg", + "float16_t *base", + "int64_t vnum", + "svfloat16x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H - Zdata3.H}" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4H" + ], + [ + "ST4H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4_vnum[_f32]", + "arguments": [ + "svbool_t pg", + "float32_t *base", + "int64_t vnum", + "svfloat32x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S - Zdata3.S}" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4W" + ], + [ + "ST4W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4_vnum[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "int64_t vnum", + "svfloat64x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D - Zdata3.D}" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4D" + ], + [ + "ST4D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4_vnum[_s16]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "int64_t vnum", + "svint16x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H - Zdata3.H}" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4H" + ], + [ + "ST4H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4_vnum[_s32]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "int64_t vnum", + "svint32x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S - Zdata3.S}" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4W" + ], + [ + "ST4W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4_vnum[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "int64_t vnum", + "svint64x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D - Zdata3.D}" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4D" + ], + [ + "ST4D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4_vnum[_s8]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "int64_t vnum", + "svint8x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.B - Zdata3.B}" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4B" + ], + [ + "ST4B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4_vnum[_u16]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "int64_t vnum", + "svuint16x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.H - Zdata3.H}" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4H" + ], + [ + "ST4H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4_vnum[_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "int64_t vnum", + "svuint32x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.S - Zdata3.S}" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4W" + ], + [ + "ST4W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4_vnum[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "int64_t vnum", + "svuint64x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.D - Zdata3.D}" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4D" + ], + [ + "ST4D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svst4_vnum[_u8]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "int64_t vnum", + "svuint8x4_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "{Zdata0.B - Zdata3.B}" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST4B" + ], + [ + "ST4B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1[_f16]", + "arguments": [ + "svbool_t pg", + "float16_t *base", + "svfloat16_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ], + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_f16_x2]", + "arguments": [ + "svcount_t png", + "float16_t * rn", + "svfloat16x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H, Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_f16_x4]", + "arguments": [ + "svcount_t png", + "float16_t * rn", + "svfloat16x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H - Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1[_f32]", + "arguments": [ + "svbool_t pg", + "float32_t *base", + "svfloat32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ], + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_f32_x2]", + "arguments": [ + "svcount_t png", + "float32_t * rn", + "svfloat32x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S, Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_f32_x4]", + "arguments": [ + "svcount_t png", + "float32_t * rn", + "svfloat32x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S - Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ], + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_f64_x2]", + "arguments": [ + "svcount_t png", + "float64_t * rn", + "svfloat64x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D, Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_f64_x4]", + "arguments": [ + "svcount_t png", + "float64_t * rn", + "svfloat64x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D - Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1[_s16]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svint16_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ], + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_s16_x2]", + "arguments": [ + "svcount_t png", + "int16_t * rn", + "svint16x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H, Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_s16_x4]", + "arguments": [ + "svcount_t png", + "int16_t * rn", + "svint16x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H - Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1[_s32]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ], + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_s32_x2]", + "arguments": [ + "svcount_t png", + "int32_t * rn", + "svint32x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S, Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_s32_x4]", + "arguments": [ + "svcount_t png", + "int32_t * rn", + "svint32x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S - Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ], + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_s64_x2]", + "arguments": [ + "svcount_t png", + "int64_t * rn", + "svint64x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D, Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_s64_x4]", + "arguments": [ + "svcount_t png", + "int64_t * rn", + "svint64x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D - Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1[_s8]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "svint8_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ], + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_s8_x2]", + "arguments": [ + "svcount_t png", + "int8_t * rn", + "svint8x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.B, Zreg2.B }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_s8_x4]", + "arguments": [ + "svcount_t png", + "int8_t * rn", + "svint8x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.B - Zreg2.B }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1[_u16]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svuint16_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ], + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_u16_x2]", + "arguments": [ + "svcount_t png", + "uint16_t * rn", + "svuint16x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H, Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_u16_x4]", + "arguments": [ + "svcount_t png", + "uint16_t * rn", + "svuint16x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H - Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1[_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ], + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_u32_x2]", + "arguments": [ + "svcount_t png", + "uint32_t * rn", + "svuint32x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S, Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_u32_x4]", + "arguments": [ + "svcount_t png", + "uint32_t * rn", + "svuint32x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S - Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ], + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_u64_x2]", + "arguments": [ + "svcount_t png", + "uint64_t * rn", + "svuint64x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D, Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_u64_x4]", + "arguments": [ + "svcount_t png", + "uint64_t * rn", + "svuint64x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D - Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1[_u8]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "svuint8_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ], + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_u8_x2]", + "arguments": [ + "svcount_t png", + "uint8_t * rn", + "svuint8x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.B, Zreg2.B }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1[_u8_x4]", + "arguments": [ + "svcount_t png", + "uint8_t * rn", + "svuint8x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg1" + }, + "zt": { + "Z multi-vector": "{ Zreg1.B - Zreg2.B }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u32base]_index[_f32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index", + "svfloat32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u32base]_index[_s32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u32base]_index[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u32base]_offset[_f32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset", + "svfloat32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u32base]_offset[_s32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u32base]_offset[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u32base_f32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "svfloat32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u32base_s32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u32base_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u64base]_index[_f64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u64base]_index[_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u64base]_index[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "index * 8": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u64base]_offset[_f64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u64base]_offset[_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u64base]_offset[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u64base_f64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u64base_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter[_u64base_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter_[s64]index[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "svint64_t indices", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices * 8": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter_[s64]index[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "svint64_t indices", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices * 8": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter_[s64]index[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "svint64_t indices", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices * 8": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter_[s64]offset[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "svint64_t offsets", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter_[s64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "svint64_t offsets", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter_[s64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "svint64_t offsets", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter_[u32]offset[_f32]", + "arguments": [ + "svbool_t pg", + "float32_t *base", + "svuint32_t offsets", + "svfloat32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter_[u32]offset[_s32]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svuint32_t offsets", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter_[u32]offset[_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svuint32_t offsets", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter_[u64]index[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "svuint64_t indices", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices * 8": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter_[u64]index[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "svuint64_t indices", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices * 8": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter_[u64]index[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "svuint64_t indices", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices * 8": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter_[u64]offset[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "svuint64_t offsets", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter_[u64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "svuint64_t offsets", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_scatter_[u64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "svuint64_t offsets", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1_vnum[_f16]", + "arguments": [ + "svbool_t pg", + "float16_t *base", + "int64_t vnum", + "svfloat16_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.H" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ], + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_f16_x2]", + "arguments": [ + "svcount_t png", + "float16_t * rn", + "int64_t vnum", + "svfloat16x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H, Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_f16_x4]", + "arguments": [ + "svcount_t png", + "float16_t * rn", + "int64_t vnum", + "svfloat16x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H - Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1_vnum[_f32]", + "arguments": [ + "svbool_t pg", + "float32_t *base", + "int64_t vnum", + "svfloat32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ], + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_f32_x2]", + "arguments": [ + "svcount_t png", + "float32_t * rn", + "int64_t vnum", + "svfloat32x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S, Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_f32_x4]", + "arguments": [ + "svcount_t png", + "float32_t * rn", + "int64_t vnum", + "svfloat32x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S - Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1_vnum[_f64]", + "arguments": [ + "svbool_t pg", + "float64_t *base", + "int64_t vnum", + "svfloat64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ], + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_f64_x2]", + "arguments": [ + "svcount_t png", + "float64_t * rn", + "int64_t vnum", + "svfloat64x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D, Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_f64_x4]", + "arguments": [ + "svcount_t png", + "float64_t * rn", + "int64_t vnum", + "svfloat64x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D - Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1_vnum[_s16]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "int64_t vnum", + "svint16_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.H" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ], + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_s16_x2]", + "arguments": [ + "svcount_t png", + "int16_t * rn", + "int64_t vnum", + "svint16x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H, Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_s16_x4]", + "arguments": [ + "svcount_t png", + "int16_t * rn", + "int64_t vnum", + "svint16x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H - Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1_vnum[_s32]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "int64_t vnum", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ], + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_s32_x2]", + "arguments": [ + "svcount_t png", + "int32_t * rn", + "int64_t vnum", + "svint32x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S, Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_s32_x4]", + "arguments": [ + "svcount_t png", + "int32_t * rn", + "int64_t vnum", + "svint32x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S - Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1_vnum[_s64]", + "arguments": [ + "svbool_t pg", + "int64_t *base", + "int64_t vnum", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ], + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_s64_x2]", + "arguments": [ + "svcount_t png", + "int64_t * rn", + "int64_t vnum", + "svint64x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D, Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_s64_x4]", + "arguments": [ + "svcount_t png", + "int64_t * rn", + "int64_t vnum", + "svint64x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D - Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1_vnum[_s8]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "int64_t vnum", + "svint8_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.B" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ], + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_s8_x2]", + "arguments": [ + "svcount_t png", + "int8_t * rn", + "int64_t vnum", + "svint8x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.B, Zreg2.B }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_s8_x4]", + "arguments": [ + "svcount_t png", + "int8_t * rn", + "int64_t vnum", + "svint8x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.B - Zreg2.B }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1_vnum[_u16]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "int64_t vnum", + "svuint16_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.H" + }, + "pg": { + "register": "Pg.H" + }, + "vnum * svcnth()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ], + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_u16_x2]", + "arguments": [ + "svcount_t png", + "uint16_t * rn", + "int64_t vnum", + "svuint16x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H, Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_u16_x4]", + "arguments": [ + "svcount_t png", + "uint16_t * rn", + "int64_t vnum", + "svuint16x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.H - Zreg2.H }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1_vnum[_u32]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "int64_t vnum", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + }, + "vnum * svcntw()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ], + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_u32_x2]", + "arguments": [ + "svcount_t png", + "uint32_t * rn", + "int64_t vnum", + "svuint32x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S, Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_u32_x4]", + "arguments": [ + "svcount_t png", + "uint32_t * rn", + "int64_t vnum", + "svuint32x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.S - Zreg2.S }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1_vnum[_u64]", + "arguments": [ + "svbool_t pg", + "uint64_t *base", + "int64_t vnum", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + }, + "vnum * svcntd()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1D" + ], + [ + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_u64_x2]", + "arguments": [ + "svcount_t png", + "uint64_t * rn", + "int64_t vnum", + "svuint64x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D, Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_u64_x4]", + "arguments": [ + "svcount_t png", + "uint64_t * rn", + "int64_t vnum", + "svuint64x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.D - Zreg2.D }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1D" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svstnt1_vnum[_u8]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "int64_t vnum", + "svuint8_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.B" + }, + "pg": { + "register": "Pg.B" + }, + "vnum * svcntb()": { + "register": "Xindex" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ], + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_u8_x2]", + "arguments": [ + "svcount_t png", + "uint8_t * rn", + "int64_t vnum", + "svuint8x2_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.B, Zreg2.B }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1_vnum[_u8_x4]", + "arguments": [ + "svcount_t png", + "uint8_t * rn", + "int64_t vnum", + "svuint8x4_t zt" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "png": { + "register": "PNreg1" + }, + "rn": { + "register": "Xreg2" + }, + "vnum": { + "register": "Xreg3" + }, + "zt": { + "Z multi-vector": "{ Zreg1.B - Zreg2.B }" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "RDVL", + "MADD", + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1b_scatter[_u32base]_offset[_s32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1b_scatter[_u32base]_offset[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1b_scatter[_u32base_s32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1b_scatter[_u32base_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1b_scatter[_u64base]_offset[_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1b_scatter[_u64base]_offset[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1b_scatter[_u64base_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1b_scatter[_u64base_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1b_scatter_[s64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "svint64_t offsets", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1b_scatter_[s64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "svint64_t offsets", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1b_scatter_[u32]offset[_s32]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "svuint32_t offsets", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1b_scatter_[u32]offset[_u32]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "svuint32_t offsets", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1b_scatter_[u64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "int8_t *base", + "svuint64_t offsets", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1b_scatter_[u64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "uint8_t *base", + "svuint64_t offsets", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1B" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter[_u32base]_index[_s32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter[_u32base]_index[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t index", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter[_u32base]_offset[_s32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter[_u32base]_offset[_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "int64_t offset", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter[_u32base_s32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter[_u32base_u32]", + "arguments": [ + "svbool_t pg", + "svuint32_t bases", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.S" + }, + "data": { + "register": "Zdata.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter[_u64base]_index[_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter[_u64base]_index[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "index * 2": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter[_u64base]_offset[_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter[_u64base]_offset[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter[_u64base_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter[_u64base_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter_[s64]index[_s64]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svint64_t indices", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices * 2": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter_[s64]index[_u64]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svint64_t indices", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices * 2": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter_[s64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svint64_t offsets", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter_[s64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svint64_t offsets", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter_[u32]offset[_s32]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svuint32_t offsets", + "svint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter_[u32]offset[_u32]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svuint32_t offsets", + "svuint32_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.S" + }, + "offsets": { + "register": "Zoffsets.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter_[u64]index[_s64]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svuint64_t indices", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices * 2": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter_[u64]index[_u64]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svuint64_t indices", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices * 2": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter_[u64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "int16_t *base", + "svuint64_t offsets", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1h_scatter_[u64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "uint16_t *base", + "svuint64_t offsets", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1H" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1w_scatter[_u64base]_index[_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1w_scatter[_u64base]_index[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t index", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "index * 4": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1w_scatter[_u64base]_offset[_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1w_scatter[_u64base]_offset[_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "int64_t offset", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "offset": { + "register": "Xoffset" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1w_scatter[_u64base_s64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1w_scatter[_u64base_u64]", + "arguments": [ + "svbool_t pg", + "svuint64_t bases", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "bases": { + "register": "Zbases.D" + }, + "data": { + "register": "Zdata.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1w_scatter_[s64]index[_s64]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svint64_t indices", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices * 4": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1w_scatter_[s64]index[_u64]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svint64_t indices", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices * 4": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1w_scatter_[s64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svint64_t offsets", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1w_scatter_[s64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svint64_t offsets", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1w_scatter_[u64]index[_s64]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svuint64_t indices", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices * 4": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1w_scatter_[u64]index[_u64]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svuint64_t indices", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "indices * 4": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1w_scatter_[u64]offset[_s64]", + "arguments": [ + "svbool_t pg", + "int32_t *base", + "svuint64_t offsets", + "svint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svstnt1w_scatter_[u64]offset[_u64]", + "arguments": [ + "svbool_t pg", + "uint32_t *base", + "svuint64_t offsets", + "svuint64_t data" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "base": { + "register": "Xbase" + }, + "data": { + "register": "Zdata.D" + }, + "offsets": { + "register": "Zoffsets.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STNT1W" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUB" + ], + [ + "MOVPRFX", + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUB" + ], + [ + "FSUBR" + ], + [ + "FSUB" + ], + [ + "MOVPRFX", + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSUB" + ], + [ + "MOVPRFX", + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUB" + ], + [ + "MOVPRFX", + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUB" + ], + [ + "FSUBR" + ], + [ + "FSUB" + ], + [ + "MOVPRFX", + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSUB" + ], + [ + "MOVPRFX", + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUB" + ], + [ + "MOVPRFX", + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUB" + ], + [ + "FSUBR" + ], + [ + "FSUB" + ], + [ + "MOVPRFX", + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSUB" + ], + [ + "MOVPRFX", + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUB" + ], + [ + "FADD" + ], + [ + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUB" + ], + [ + "FADD" + ], + [ + "FSUB" + ], + [ + "FSUBR" + ], + [ + "FSUB" + ], + [ + "MOVPRFX", + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSUB" + ], + [ + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FSUB" + ], + [ + "MOVPRFX", + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUB" + ], + [ + "FADD" + ], + [ + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUB" + ], + [ + "FADD" + ], + [ + "FSUB" + ], + [ + "FSUBR" + ], + [ + "FSUB" + ], + [ + "MOVPRFX", + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSUB" + ], + [ + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FSUB" + ], + [ + "MOVPRFX", + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUB" + ], + [ + "FADD" + ], + [ + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUB" + ], + [ + "FADD" + ], + [ + "FSUB" + ], + [ + "FSUBR" + ], + [ + "FSUB" + ], + [ + "MOVPRFX", + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSUB" + ], + [ + "MOVPRFX", + "FADD" + ], + [ + "MOVPRFX", + "FSUB" + ], + [ + "MOVPRFX", + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "ADD" + ], + [ + "SUB" + ], + [ + "SUBR" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUB" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "ADD" + ], + [ + "SUB" + ], + [ + "SUBR" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUB" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "ADD" + ], + [ + "SUB" + ], + [ + "SUBR" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUB" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "ADD" + ], + [ + "SUB" + ], + [ + "SUBR" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUB" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "ADD" + ], + [ + "SUB" + ], + [ + "SUBR" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUB" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "ADD" + ], + [ + "SUB" + ], + [ + "SUBR" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUB" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "ADD" + ], + [ + "SUB" + ], + [ + "SUBR" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUB" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "ADD" + ], + [ + "SUB" + ], + [ + "SUBR" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUB" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "SUBR" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUB" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "SUBR" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUB" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "SUBR" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUB" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "SUBR" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUB" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "SUBR" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUB" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "SUBR" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUB" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "SUBR" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUB" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUB" + ], + [ + "SUBR" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsub[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUB" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnb[_n_s16]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnb[_n_s32]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnb[_n_s64]", + "arguments": [ + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnb[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnb[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnb[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnb[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnb[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnb[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnb[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnb[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnb[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnt[_n_s16]", + "arguments": [ + "svint8_t even", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnt[_n_s32]", + "arguments": [ + "svint16_t even", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnt[_n_s64]", + "arguments": [ + "svint32_t even", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnt[_n_u16]", + "arguments": [ + "svuint8_t even", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnt[_n_u32]", + "arguments": [ + "svuint16_t even", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnt[_n_u64]", + "arguments": [ + "svuint32_t even", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnt[_s16]", + "arguments": [ + "svint8_t even", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnt[_s32]", + "arguments": [ + "svint16_t even", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnt[_s64]", + "arguments": [ + "svint32_t even", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnt[_u16]", + "arguments": [ + "svuint8_t even", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.B" + }, + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnt[_u32]", + "arguments": [ + "svuint16_t even", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.H" + }, + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubhnt[_u64]", + "arguments": [ + "svuint32_t even", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "even": { + "register": "Ztied.S" + }, + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBHNT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublb[_n_s16]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublb[_n_s32]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublb[_n_s64]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublb[_n_u16]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublb[_n_u32]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublb[_n_u64]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublb[_s16]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublb[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublb[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublb[_u16]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublb[_u32]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublb[_u64]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBLB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublbt[_n_s16]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublbt[_n_s32]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublbt[_n_s64]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublbt[_s16]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublbt[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublbt[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLBT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublt[_n_s16]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublt[_n_s32]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublt[_n_s64]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublt[_n_u16]", + "arguments": [ + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublt[_n_u32]", + "arguments": [ + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublt[_n_u64]", + "arguments": [ + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublt[_s16]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublt[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublt[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublt[_u16]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublt[_u32]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsublt[_u64]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBLT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubltb[_n_s16]", + "arguments": [ + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubltb[_n_s32]", + "arguments": [ + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubltb[_n_s64]", + "arguments": [ + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubltb[_s16]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubltb[_s32]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLTB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubltb[_s64]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBLTB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUBR" + ], + [ + "MOVPRFX", + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUBR" + ], + [ + "FSUB" + ], + [ + "FSUB" + ], + [ + "MOVPRFX", + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSUBR" + ], + [ + "MOVPRFX", + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUBR" + ], + [ + "MOVPRFX", + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUBR" + ], + [ + "FSUB" + ], + [ + "FSUB" + ], + [ + "MOVPRFX", + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSUBR" + ], + [ + "MOVPRFX", + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUBR" + ], + [ + "MOVPRFX", + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUBR" + ], + [ + "FSUB" + ], + [ + "FSUB" + ], + [ + "MOVPRFX", + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSUBR" + ], + [ + "MOVPRFX", + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_f16]_m", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUBR" + ], + [ + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_f16]_x", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUBR" + ], + [ + "FSUBR" + ], + [ + "FSUB" + ], + [ + "FSUB" + ], + [ + "MOVPRFX", + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_f16]_z", + "arguments": [ + "svbool_t pg", + "svfloat16_t op1", + "float16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSUBR" + ], + [ + "MOVPRFX", + "FSUBR" + ], + [ + "MOVPRFX", + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_f32]_m", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUBR" + ], + [ + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_f32]_x", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUBR" + ], + [ + "FSUBR" + ], + [ + "FSUB" + ], + [ + "FSUB" + ], + [ + "MOVPRFX", + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_f32]_z", + "arguments": [ + "svbool_t pg", + "svfloat32_t op1", + "float32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSUBR" + ], + [ + "MOVPRFX", + "FSUBR" + ], + [ + "MOVPRFX", + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_f64]_m", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUBR" + ], + [ + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_f64]_x", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSUBR" + ], + [ + "FSUBR" + ], + [ + "FSUB" + ], + [ + "FSUB" + ], + [ + "MOVPRFX", + "FSUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_f64]_z", + "arguments": [ + "svbool_t pg", + "svfloat64_t op1", + "float64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "FSUBR" + ], + [ + "MOVPRFX", + "FSUBR" + ], + [ + "MOVPRFX", + "FSUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "SUBR" + ], + [ + "SUB" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUBR" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "SUBR" + ], + [ + "SUB" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUBR" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "SUBR" + ], + [ + "SUB" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUBR" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "SUBR" + ], + [ + "SUB" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUBR" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]|Ztied2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "SUBR" + ], + [ + "SUB" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUBR" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]|Ztied2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "SUBR" + ], + [ + "SUB" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUBR" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]|Ztied2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "SUBR" + ], + [ + "SUB" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUBR" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]|Ztied2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "SUBR" + ], + [ + "SUB" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_n_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUBR" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "SUB" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUBR" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "SUB" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUBR" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "SUB" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUBR" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "SUB" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUBR" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_u16]_m", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_u16]_x", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "SUB" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_u16]_z", + "arguments": [ + "svbool_t pg", + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUBR" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_u32]_m", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_u32]_x", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "SUB" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_u32]_z", + "arguments": [ + "svbool_t pg", + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUBR" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_u64]_m", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_u64]_x", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "SUB" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_u64]_z", + "arguments": [ + "svbool_t pg", + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUBR" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_u8]_m", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "MOVPRFX", + "SUBR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_u8]_x", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUBR" + ], + [ + "SUB" + ], + [ + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsubr[_u8]_z", + "arguments": [ + "svbool_t pg", + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUBR" + ], + [ + "MOVPRFX", + "SUB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwb[_n_s16]", + "arguments": [ + "svint16_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwb[_n_s32]", + "arguments": [ + "svint32_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwb[_n_s64]", + "arguments": [ + "svint64_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwb[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwb[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwb[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwb[_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwb[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwb[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwb[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwb[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwb[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBWB" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwt[_n_s16]", + "arguments": [ + "svint16_t op1", + "int8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwt[_n_s32]", + "arguments": [ + "svint32_t op1", + "int16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwt[_n_s64]", + "arguments": [ + "svint64_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwt[_n_u16]", + "arguments": [ + "svuint16_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwt[_n_u32]", + "arguments": [ + "svuint32_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwt[_n_u64]", + "arguments": [ + "svuint64_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwt[_s16]", + "arguments": [ + "svint16_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwt[_s32]", + "arguments": [ + "svint32_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwt[_s64]", + "arguments": [ + "svint64_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SSUBWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwt[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwt[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBWT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svsubwt[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USUBWT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsudot[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint8_t op2", + "uint8_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USDOT" + ], + [ + "MOVPRFX", + "USDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsudot[_s32]", + "arguments": [ + "svint32_t op1", + "svint8_t op2", + "svuint8_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USDOT" + ], + [ + "MOVPRFX", + "USDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svsudot_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svint8_t op2", + "svuint8_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUDOT" + ], + [ + "MOVPRFX", + "SUDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbl2[_f16]", + "arguments": [ + "svfloat16x2_t data", + "svuint16_t indices" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "{Zdata0.H, Zdata1.H}" + }, + "indices": { + "register": "Zindices.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbl2[_f32]", + "arguments": [ + "svfloat32x2_t data", + "svuint32_t indices" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "{Zdata0.S, Zdata1.S}" + }, + "indices": { + "register": "Zindices.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbl2[_f64]", + "arguments": [ + "svfloat64x2_t data", + "svuint64_t indices" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "{Zdata0.D, Zdata1.D}" + }, + "indices": { + "register": "Zindices.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbl2[_s16]", + "arguments": [ + "svint16x2_t data", + "svuint16_t indices" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "{Zdata0.H, Zdata1.H}" + }, + "indices": { + "register": "Zindices.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbl2[_s32]", + "arguments": [ + "svint32x2_t data", + "svuint32_t indices" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "{Zdata0.S, Zdata1.S}" + }, + "indices": { + "register": "Zindices.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbl2[_s64]", + "arguments": [ + "svint64x2_t data", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "{Zdata0.D, Zdata1.D}" + }, + "indices": { + "register": "Zindices.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbl2[_s8]", + "arguments": [ + "svint8x2_t data", + "svuint8_t indices" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "{Zdata0.B, Zdata1.B}" + }, + "indices": { + "register": "Zindices.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbl2[_u16]", + "arguments": [ + "svuint16x2_t data", + "svuint16_t indices" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "{Zdata0.H, Zdata1.H}" + }, + "indices": { + "register": "Zindices.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbl2[_u32]", + "arguments": [ + "svuint32x2_t data", + "svuint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "{Zdata0.S, Zdata1.S}" + }, + "indices": { + "register": "Zindices.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbl2[_u64]", + "arguments": [ + "svuint64x2_t data", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "{Zdata0.D, Zdata1.D}" + }, + "indices": { + "register": "Zindices.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbl2[_u8]", + "arguments": [ + "svuint8x2_t data", + "svuint8_t indices" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "{Zdata0.B, Zdata1.B}" + }, + "indices": { + "register": "Zindices.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtbl[_f16]", + "arguments": [ + "svfloat16_t data", + "svuint16_t indices" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "indices": { + "register": "Zindices.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtbl[_f32]", + "arguments": [ + "svfloat32_t data", + "svuint32_t indices" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "indices": { + "register": "Zindices.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtbl[_f64]", + "arguments": [ + "svfloat64_t data", + "svuint64_t indices" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtbl[_s16]", + "arguments": [ + "svint16_t data", + "svuint16_t indices" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "indices": { + "register": "Zindices.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtbl[_s32]", + "arguments": [ + "svint32_t data", + "svuint32_t indices" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "indices": { + "register": "Zindices.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtbl[_s64]", + "arguments": [ + "svint64_t data", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtbl[_s8]", + "arguments": [ + "svint8_t data", + "svuint8_t indices" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.B" + }, + "indices": { + "register": "Zindices.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtbl[_u16]", + "arguments": [ + "svuint16_t data", + "svuint16_t indices" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "indices": { + "register": "Zindices.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtbl[_u32]", + "arguments": [ + "svuint32_t data", + "svuint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "indices": { + "register": "Zindices.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtbl[_u64]", + "arguments": [ + "svuint64_t data", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "indices": { + "register": "Zindices.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtbl[_u8]", + "arguments": [ + "svuint8_t data", + "svuint8_t indices" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.B" + }, + "indices": { + "register": "Zindices.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbx[_f16]", + "arguments": [ + "svfloat16_t fallback", + "svfloat16_t data", + "svuint16_t indices" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Ztied.H" + }, + "indices": { + "register": "Zindices.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbx[_f32]", + "arguments": [ + "svfloat32_t fallback", + "svfloat32_t data", + "svuint32_t indices" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Ztied.S" + }, + "indices": { + "register": "Zindices.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbx[_f64]", + "arguments": [ + "svfloat64_t fallback", + "svfloat64_t data", + "svuint64_t indices" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Ztied.D" + }, + "indices": { + "register": "Zindices.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbx[_s16]", + "arguments": [ + "svint16_t fallback", + "svint16_t data", + "svuint16_t indices" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Ztied.H" + }, + "indices": { + "register": "Zindices.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbx[_s32]", + "arguments": [ + "svint32_t fallback", + "svint32_t data", + "svuint32_t indices" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Ztied.S" + }, + "indices": { + "register": "Zindices.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbx[_s64]", + "arguments": [ + "svint64_t fallback", + "svint64_t data", + "svuint64_t indices" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Ztied.D" + }, + "indices": { + "register": "Zindices.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbx[_s8]", + "arguments": [ + "svint8_t fallback", + "svint8_t data", + "svuint8_t indices" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Ztied.B" + }, + "indices": { + "register": "Zindices.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbx[_u16]", + "arguments": [ + "svuint16_t fallback", + "svuint16_t data", + "svuint16_t indices" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.H" + }, + "fallback": { + "register": "Ztied.H" + }, + "indices": { + "register": "Zindices.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbx[_u32]", + "arguments": [ + "svuint32_t fallback", + "svuint32_t data", + "svuint32_t indices" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.S" + }, + "fallback": { + "register": "Ztied.S" + }, + "indices": { + "register": "Zindices.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbx[_u64]", + "arguments": [ + "svuint64_t fallback", + "svuint64_t data", + "svuint64_t indices" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.D" + }, + "fallback": { + "register": "Ztied.D" + }, + "indices": { + "register": "Zindices.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBX" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svtbx[_u8]", + "arguments": [ + "svuint8_t fallback", + "svuint8_t data", + "svuint8_t indices" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "data": { + "register": "Zdata.B" + }, + "fallback": { + "register": "Ztied.B" + }, + "indices": { + "register": "Zindices.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TBX" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtmad[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FTMAD" + ], + [ + "MOVPRFX", + "FTMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtmad[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FTMAD" + ], + [ + "MOVPRFX", + "FTMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtmad[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 0, + "maximum": 7 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FTMAD" + ], + [ + "MOVPRFX", + "FTMAD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1_b16", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.H" + }, + "op2": { + "register": "Pop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1_b32", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.S" + }, + "op2": { + "register": "Pop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1_b64", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.D" + }, + "op2": { + "register": "Pop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1_b8", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1q[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1q[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1q[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1q[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1q[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1q[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1q[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1q[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1q[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1q[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn1q[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2_b16", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.H" + }, + "op2": { + "register": "Pop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2_b32", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.S" + }, + "op2": { + "register": "Pop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2_b64", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.D" + }, + "op2": { + "register": "Pop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2_b8", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2q[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2q[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2q[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2q[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2q[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2q[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2q[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2q[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2q[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2q[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtrn2q[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtsmul[_f16]", + "arguments": [ + "svfloat16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FTSMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtsmul[_f32]", + "arguments": [ + "svfloat32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FTSMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtsmul[_f64]", + "arguments": [ + "svfloat64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FTSMUL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtssel[_f16]", + "arguments": [ + "svfloat16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FTSSEL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtssel[_f32]", + "arguments": [ + "svfloat32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FTSSEL" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svtssel[_f64]", + "arguments": [ + "svfloat64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FTSSEL" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svundef2_b", + "arguments": [], + "return_type": { + "value": "svboolx2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef2_f16", + "arguments": [], + "return_type": { + "value": "svfloat16x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef2_f32", + "arguments": [], + "return_type": { + "value": "svfloat32x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef2_f64", + "arguments": [], + "return_type": { + "value": "svfloat64x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef2_s16", + "arguments": [], + "return_type": { + "value": "svint16x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef2_s32", + "arguments": [], + "return_type": { + "value": "svint32x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef2_s64", + "arguments": [], + "return_type": { + "value": "svint64x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef2_s8", + "arguments": [], + "return_type": { + "value": "svint8x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef2_u16", + "arguments": [], + "return_type": { + "value": "svuint16x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef2_u32", + "arguments": [], + "return_type": { + "value": "svuint32x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef2_u64", + "arguments": [], + "return_type": { + "value": "svuint64x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef2_u8", + "arguments": [], + "return_type": { + "value": "svuint8x2_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef3_f16", + "arguments": [], + "return_type": { + "value": "svfloat16x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef3_f32", + "arguments": [], + "return_type": { + "value": "svfloat32x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef3_f64", + "arguments": [], + "return_type": { + "value": "svfloat64x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef3_s16", + "arguments": [], + "return_type": { + "value": "svint16x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef3_s32", + "arguments": [], + "return_type": { + "value": "svint32x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef3_s64", + "arguments": [], + "return_type": { + "value": "svint64x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef3_s8", + "arguments": [], + "return_type": { + "value": "svint8x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef3_u16", + "arguments": [], + "return_type": { + "value": "svuint16x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef3_u32", + "arguments": [], + "return_type": { + "value": "svuint32x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef3_u64", + "arguments": [], + "return_type": { + "value": "svuint64x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef3_u8", + "arguments": [], + "return_type": { + "value": "svuint8x3_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svundef4_b", + "arguments": [], + "return_type": { + "value": "svboolx4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef4_f16", + "arguments": [], + "return_type": { + "value": "svfloat16x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef4_f32", + "arguments": [], + "return_type": { + "value": "svfloat32x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef4_f64", + "arguments": [], + "return_type": { + "value": "svfloat64x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef4_s16", + "arguments": [], + "return_type": { + "value": "svint16x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef4_s32", + "arguments": [], + "return_type": { + "value": "svint32x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef4_s64", + "arguments": [], + "return_type": { + "value": "svint64x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef4_s8", + "arguments": [], + "return_type": { + "value": "svint8x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef4_u16", + "arguments": [], + "return_type": { + "value": "svuint16x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef4_u32", + "arguments": [], + "return_type": { + "value": "svuint32x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef4_u64", + "arguments": [], + "return_type": { + "value": "svuint64x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef4_u8", + "arguments": [], + "return_type": { + "value": "svuint8x4_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef_f16", + "arguments": [], + "return_type": { + "value": "svfloat16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef_f32", + "arguments": [], + "return_type": { + "value": "svfloat32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef_f64", + "arguments": [], + "return_type": { + "value": "svfloat64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef_s16", + "arguments": [], + "return_type": { + "value": "svint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef_s32", + "arguments": [], + "return_type": { + "value": "svint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef_s64", + "arguments": [], + "return_type": { + "value": "svint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef_s8", + "arguments": [], + "return_type": { + "value": "svint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef_u16", + "arguments": [], + "return_type": { + "value": "svuint16_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef_u32", + "arguments": [], + "return_type": { + "value": "svuint32_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef_u64", + "arguments": [], + "return_type": { + "value": "svuint64_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svundef_u8", + "arguments": [], + "return_type": { + "value": "svuint8_t" + }, + "Architectures": [ + "A64" + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svunpkhi[_b]", + "arguments": [ + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Pop.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PUNPKHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svunpkhi[_s16]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUNPKHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svunpkhi[_s32]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUNPKHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svunpkhi[_s64]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUNPKHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svunpkhi[_u16]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UUNPKHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svunpkhi[_u32]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UUNPKHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svunpkhi[_u64]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UUNPKHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svunpklo[_b]", + "arguments": [ + "svbool_t op" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Pop.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "PUNPKLO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svunpklo[_s16]", + "arguments": [ + "svint8_t op" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUNPKLO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svunpklo[_s32]", + "arguments": [ + "svint16_t op" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUNPKLO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svunpklo[_s64]", + "arguments": [ + "svint32_t op" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUNPKLO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svunpklo[_u16]", + "arguments": [ + "svuint8_t op" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UUNPKLO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svunpklo[_u32]", + "arguments": [ + "svuint16_t op" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UUNPKLO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svunpklo[_u64]", + "arguments": [ + "svuint32_t op" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op": { + "register": "Zop.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UUNPKLO" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_n_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ], + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_n_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_n_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "uint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H[*]" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_n_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ], + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_n_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_n_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S[*]" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_n_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ], + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_n_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_n_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D[*]" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_n_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ], + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_n_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Ztied1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SQADD" + ], + [ + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_n_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "uint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B[*]" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_s16]_m", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ], + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_s16]_x", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ], + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_s16]_z", + "arguments": [ + "svbool_t pg", + "svint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "pg": { + "register": "Pg.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_s32]_m", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ], + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_s32]_x", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ], + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_s32]_z", + "arguments": [ + "svbool_t pg", + "svint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "pg": { + "register": "Pg.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_s64]_m", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ], + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_s64]_x", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ], + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_s64]_z", + "arguments": [ + "svbool_t pg", + "svint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "pg": { + "register": "Pg.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_s8]_m", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ], + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_s8]_x", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SUQADD" + ], + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svuqadd[_s8]_z", + "arguments": [ + "svbool_t pg", + "svint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "pg": { + "register": "Pg.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "MOVPRFX", + "SUQADD" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svusdot[_n_s32]", + "arguments": [ + "svint32_t op1", + "svuint8_t op2", + "int8_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USDOT" + ], + [ + "MOVPRFX", + "USDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svusdot[_s32]", + "arguments": [ + "svint32_t op1", + "svuint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USDOT" + ], + [ + "MOVPRFX", + "USDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svusdot_lane[_s32]", + "arguments": [ + "svint32_t op1", + "svuint8_t op2", + "svint8_t op3", + "uint64_t imm_index" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm_index": { + "minimum": 0, + "maximum": 3 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USDOT" + ], + [ + "MOVPRFX", + "USDOT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svusmmla[_s32]", + "arguments": [ + "svint32_t op1", + "svuint8_t op2", + "svint8_t op3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "USMMLA" + ], + [ + "MOVPRFX", + "USMMLA" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1_b16", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.H" + }, + "op2": { + "register": "Pop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1_b32", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.S" + }, + "op2": { + "register": "Pop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1_b64", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.D" + }, + "op2": { + "register": "Pop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1_b8", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1q[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1q[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1q[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1q[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1q[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1q[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1q[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1q[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1q[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1q[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp1q[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2_b16", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.H" + }, + "op2": { + "register": "Pop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2_b32", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.S" + }, + "op2": { + "register": "Pop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2_b64", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.D" + }, + "op2": { + "register": "Pop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2_b8", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2q[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2q[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2q[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2q[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2q[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2q[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2q[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2q[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2q[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2q[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svuzp2q[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b16[_s32]", + "arguments": [ + "int32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b16[_s64]", + "arguments": [ + "int64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b16[_s64]_x2", + "arguments": [ + "int64_t rn", + "int64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b16[_u32]", + "arguments": [ + "uint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b16[_u64]", + "arguments": [ + "uint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b16[_u64]_x2", + "arguments": [ + "uint64_t rn", + "uint64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b32[_s32]", + "arguments": [ + "int32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b32[_s64]", + "arguments": [ + "int64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b32[_s64]_x2", + "arguments": [ + "int64_t rn", + "int64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b32[_u32]", + "arguments": [ + "uint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b32[_u64]", + "arguments": [ + "uint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b32[_u64]_x2", + "arguments": [ + "uint64_t rn", + "uint64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b64[_s32]", + "arguments": [ + "int32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b64[_s64]", + "arguments": [ + "int64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b64[_s64]_x2", + "arguments": [ + "int64_t rn", + "int64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b64[_u32]", + "arguments": [ + "uint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b64[_u64]", + "arguments": [ + "uint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b64[_u64]_x2", + "arguments": [ + "uint64_t rn", + "uint64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b8[_s32]", + "arguments": [ + "int32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b8[_s64]", + "arguments": [ + "int64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b8[_s64]_x2", + "arguments": [ + "int64_t rn", + "int64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b8[_u32]", + "arguments": [ + "uint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b8[_u64]", + "arguments": [ + "uint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_b8[_u64]_x2", + "arguments": [ + "uint64_t rn", + "uint64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_c16[_s64]", + "arguments": [ + "int64_t rn", + "int64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_c16[_u64]", + "arguments": [ + "uint64_t rn", + "uint64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_c32[_s64]", + "arguments": [ + "int64_t rn", + "int64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_c32[_u64]", + "arguments": [ + "uint64_t rn", + "uint64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_c64[_s64]", + "arguments": [ + "int64_t rn", + "int64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_c64[_u64]", + "arguments": [ + "uint64_t rn", + "uint64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_c8[_s64]", + "arguments": [ + "int64_t rn", + "int64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilege_c8[_u64]", + "arguments": [ + "uint64_t rn", + "uint64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b16[_s32]", + "arguments": [ + "int32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b16[_s64]", + "arguments": [ + "int64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b16[_s64]_x2", + "arguments": [ + "int64_t rn", + "int64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b16[_u32]", + "arguments": [ + "uint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b16[_u64]", + "arguments": [ + "uint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b16[_u64]_x2", + "arguments": [ + "uint64_t rn", + "uint64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b32[_s32]", + "arguments": [ + "int32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b32[_s64]", + "arguments": [ + "int64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b32[_s64]_x2", + "arguments": [ + "int64_t rn", + "int64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b32[_u32]", + "arguments": [ + "uint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b32[_u64]", + "arguments": [ + "uint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b32[_u64]_x2", + "arguments": [ + "uint64_t rn", + "uint64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b64[_s32]", + "arguments": [ + "int32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b64[_s64]", + "arguments": [ + "int64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b64[_s64]_x2", + "arguments": [ + "int64_t rn", + "int64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b64[_u32]", + "arguments": [ + "uint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b64[_u64]", + "arguments": [ + "uint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b64[_u64]_x2", + "arguments": [ + "uint64_t rn", + "uint64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b8[_s32]", + "arguments": [ + "int32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b8[_s64]", + "arguments": [ + "int64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b8[_s64]_x2", + "arguments": [ + "int64_t rn", + "int64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b8[_u32]", + "arguments": [ + "uint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b8[_u64]", + "arguments": [ + "uint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_b8[_u64]_x2", + "arguments": [ + "uint64_t rn", + "uint64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_c16[_s64]", + "arguments": [ + "int64_t rn", + "int64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_c16[_u64]", + "arguments": [ + "uint64_t rn", + "uint64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_c32[_s64]", + "arguments": [ + "int64_t rn", + "int64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_c32[_u64]", + "arguments": [ + "uint64_t rn", + "uint64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_c64[_s64]", + "arguments": [ + "int64_t rn", + "int64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_c64[_u64]", + "arguments": [ + "uint64_t rn", + "uint64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHI" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_c8[_s64]", + "arguments": [ + "int64_t rn", + "int64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEGT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilegt_c8[_u64]", + "arguments": [ + "uint64_t rn", + "uint64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEHI" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilele_b16[_s32]", + "arguments": [ + "int32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilele_b16[_s64]", + "arguments": [ + "int64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilele_b16[_s64]_x2", + "arguments": [ + "int64_t rn", + "int64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilele_b16[_u32]", + "arguments": [ + "uint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilele_b16[_u64]", + "arguments": [ + "uint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilele_b16[_u64]_x2", + "arguments": [ + "uint64_t rn", + "uint64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilele_b32[_s32]", + "arguments": [ + "int32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilele_b32[_s64]", + "arguments": [ + "int64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilele_b32[_s64]_x2", + "arguments": [ + "int64_t rn", + "int64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilele_b32[_u32]", + "arguments": [ + "uint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilele_b32[_u64]", + "arguments": [ + "uint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilele_b32[_u64]_x2", + "arguments": [ + "uint64_t rn", + "uint64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilele_b64[_s32]", + "arguments": [ + "int32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilele_b64[_s64]", + "arguments": [ + "int64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilele_b64[_s64]_x2", + "arguments": [ + "int64_t rn", + "int64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilele_b64[_u32]", + "arguments": [ + "uint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilele_b64[_u64]", + "arguments": [ + "uint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilele_b64[_u64]_x2", + "arguments": [ + "uint64_t rn", + "uint64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilele_b8[_s32]", + "arguments": [ + "int32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilele_b8[_s64]", + "arguments": [ + "int64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilele_b8[_s64]_x2", + "arguments": [ + "int64_t rn", + "int64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELE" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilele_b8[_u32]", + "arguments": [ + "uint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilele_b8[_u64]", + "arguments": [ + "uint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilele_b8[_u64]_x2", + "arguments": [ + "uint64_t rn", + "uint64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilele_c16[_s64]", + "arguments": [ + "int64_t rn", + "int64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilele_c16[_u64]", + "arguments": [ + "uint64_t rn", + "uint64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilele_c32[_s64]", + "arguments": [ + "int64_t rn", + "int64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilele_c32[_u64]", + "arguments": [ + "uint64_t rn", + "uint64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilele_c64[_s64]", + "arguments": [ + "int64_t rn", + "int64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilele_c64[_u64]", + "arguments": [ + "uint64_t rn", + "uint64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELS" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilele_c8[_s64]", + "arguments": [ + "int64_t rn", + "int64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELE" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilele_c8[_u64]", + "arguments": [ + "uint64_t rn", + "uint64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELS" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilelt_b16[_s32]", + "arguments": [ + "int32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilelt_b16[_s64]", + "arguments": [ + "int64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilelt_b16[_s64]_x2", + "arguments": [ + "int64_t rn", + "int64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilelt_b16[_u32]", + "arguments": [ + "uint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilelt_b16[_u64]", + "arguments": [ + "uint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELO" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilelt_b16[_u64]_x2", + "arguments": [ + "uint64_t rn", + "uint64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilelt_b32[_s32]", + "arguments": [ + "int32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilelt_b32[_s64]", + "arguments": [ + "int64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilelt_b32[_s64]_x2", + "arguments": [ + "int64_t rn", + "int64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilelt_b32[_u32]", + "arguments": [ + "uint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilelt_b32[_u64]", + "arguments": [ + "uint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELO" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilelt_b32[_u64]_x2", + "arguments": [ + "uint64_t rn", + "uint64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilelt_b64[_s32]", + "arguments": [ + "int32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilelt_b64[_s64]", + "arguments": [ + "int64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilelt_b64[_s64]_x2", + "arguments": [ + "int64_t rn", + "int64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilelt_b64[_u32]", + "arguments": [ + "uint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilelt_b64[_u64]", + "arguments": [ + "uint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELO" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilelt_b64[_u64]_x2", + "arguments": [ + "uint64_t rn", + "uint64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilelt_b8[_s32]", + "arguments": [ + "int32_t op1", + "int32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilelt_b8[_s64]", + "arguments": [ + "int64_t op1", + "int64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilelt_b8[_s64]_x2", + "arguments": [ + "int64_t rn", + "int64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELT" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilelt_b8[_u32]", + "arguments": [ + "uint32_t op1", + "uint32_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Wop1" + }, + "op2": { + "register": "Wop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELO" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwhilelt_b8[_u64]", + "arguments": [ + "uint64_t op1", + "uint64_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELO" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilelt_b8[_u64]_x2", + "arguments": [ + "uint64_t rn", + "uint64_t rm" + ], + "return_type": { + "value": "svboolx2_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELO" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilelt_c16[_s64]", + "arguments": [ + "int64_t rn", + "int64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilelt_c16[_u64]", + "arguments": [ + "uint64_t rn", + "uint64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELO" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilelt_c32[_s64]", + "arguments": [ + "int64_t rn", + "int64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilelt_c32[_u64]", + "arguments": [ + "uint64_t rn", + "uint64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELO" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilelt_c64[_s64]", + "arguments": [ + "int64_t rn", + "int64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilelt_c64[_u64]", + "arguments": [ + "uint64_t rn", + "uint64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELO" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilelt_c8[_s64]", + "arguments": [ + "int64_t rn", + "int64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELT" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilelt_c8[_u64]", + "arguments": [ + "uint64_t rn", + "uint64_t rm", + "uint64_t vl" + ], + "return_type": { + "value": "svcount_t" + }, + "Arguments_Preparation": { + "rm": { + "register": "Xreg2" + }, + "rn": { + "register": "Xreg1" + }, + "vl": { + "immediate": "" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILELO" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilerw[_f16]", + "arguments": [ + "const float16_t *op1", + "const float16_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILERW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilerw[_f32]", + "arguments": [ + "const float32_t *op1", + "const float32_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILERW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilerw[_f64]", + "arguments": [ + "const float64_t *op1", + "const float64_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILERW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilerw[_s16]", + "arguments": [ + "const int16_t *op1", + "const int16_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILERW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilerw[_s32]", + "arguments": [ + "const int32_t *op1", + "const int32_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILERW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilerw[_s64]", + "arguments": [ + "const int64_t *op1", + "const int64_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILERW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilerw[_s8]", + "arguments": [ + "const int8_t *op1", + "const int8_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILERW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilerw[_u16]", + "arguments": [ + "const uint16_t *op1", + "const uint16_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILERW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilerw[_u32]", + "arguments": [ + "const uint32_t *op1", + "const uint32_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILERW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilerw[_u64]", + "arguments": [ + "const uint64_t *op1", + "const uint64_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILERW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilerw[_u8]", + "arguments": [ + "const uint8_t *op1", + "const uint8_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILERW" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilewr[_f16]", + "arguments": [ + "const float16_t *op1", + "const float16_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEWR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilewr[_f32]", + "arguments": [ + "const float32_t *op1", + "const float32_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEWR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilewr[_f64]", + "arguments": [ + "const float64_t *op1", + "const float64_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEWR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilewr[_s16]", + "arguments": [ + "const int16_t *op1", + "const int16_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEWR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilewr[_s32]", + "arguments": [ + "const int32_t *op1", + "const int32_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEWR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilewr[_s64]", + "arguments": [ + "const int64_t *op1", + "const int64_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEWR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilewr[_s8]", + "arguments": [ + "const int8_t *op1", + "const int8_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEWR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilewr[_u16]", + "arguments": [ + "const uint16_t *op1", + "const uint16_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEWR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilewr[_u32]", + "arguments": [ + "const uint32_t *op1", + "const uint32_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEWR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilewr[_u64]", + "arguments": [ + "const uint64_t *op1", + "const uint64_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEWR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svwhilewr[_u8]", + "arguments": [ + "const uint8_t *op1", + "const uint8_t *op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Xop1" + }, + "op2": { + "register": "Xop2" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WHILEWR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svwrffr", + "arguments": [ + "svbool_t op" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "op": { + "register": "Pop.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "WRFFR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svxar[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "XAR" + ], + [ + "XAR" + ], + [ + "MOVPRFX", + "XAR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svxar[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "XAR" + ], + [ + "XAR" + ], + [ + "MOVPRFX", + "XAR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svxar[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "XAR" + ], + [ + "XAR" + ], + [ + "MOVPRFX", + "XAR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svxar[_n_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "XAR" + ], + [ + "XAR" + ], + [ + "MOVPRFX", + "XAR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svxar[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 16 + }, + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H|Ztied2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "XAR" + ], + [ + "XAR" + ], + [ + "MOVPRFX", + "XAR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svxar[_n_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 32 + }, + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S|Ztied2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "XAR" + ], + [ + "XAR" + ], + [ + "MOVPRFX", + "XAR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svxar[_n_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 64 + }, + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D|Ztied2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "XAR" + ], + [ + "XAR" + ], + [ + "MOVPRFX", + "XAR" + ] + ] + }, + { + "SIMD_ISA": "SVE2", + "name": "svxar[_n_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2", + "uint64_t imm3" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "imm3": { + "minimum": 1, + "maximum": 8 + }, + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B|Ztied2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "XAR" + ], + [ + "XAR" + ], + [ + "MOVPRFX", + "XAR" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1_b16", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.H" + }, + "op2": { + "register": "Pop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1_b32", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.S" + }, + "op2": { + "register": "Pop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1_b64", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.D" + }, + "op2": { + "register": "Pop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1_b8", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1q[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1q[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1q[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1q[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1q[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1q[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1q[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1q[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1q[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1q[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip1q[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2_b16", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.H" + }, + "op2": { + "register": "Pop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2_b32", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.S" + }, + "op2": { + "register": "Pop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2_b64", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.D" + }, + "op2": { + "register": "Pop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2_b8", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_f16]", + "arguments": [ + "svfloat16_t op1", + "svfloat16_t op2" + ], + "return_type": { + "value": "svfloat16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "SVE", + "name": "svzip2q[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" ] ] }, @@ -4404,7 +207121,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vm.2S" } }, "Architectures": [ @@ -4473,7 +207190,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vm.2S" } }, "Architectures": [ @@ -4519,7 +207236,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.4S" + "register": "Vm.4S" } }, "Architectures": [ @@ -5179,6 +207896,276 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vamax_f16", + "arguments": [ + "float16x4_t vn", + "float16x4_t vm" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.4H" + }, + "vn": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMAX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vamax_f32", + "arguments": [ + "float32x2_t vn", + "float32x2_t vm" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.2S" + }, + "vn": { + "register": "Vn.2S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMAX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vamaxq_f16", + "arguments": [ + "float16x8_t vn", + "float16x8_t vm" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.8H" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMAX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vamaxq_f32", + "arguments": [ + "float32x4_t vn", + "float32x4_t vm" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.4S" + }, + "vn": { + "register": "Vn.4S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMAX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vamaxq_f64", + "arguments": [ + "float64x2_t vn", + "float64x2_t vm" + ], + "return_type": { + "value": "float64x2_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.2D" + }, + "vn": { + "register": "Vn.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMAX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vamin_f16", + "arguments": [ + "float16x4_t vn", + "float16x4_t vm" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.4H" + }, + "vn": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMIN" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vamin_f32", + "arguments": [ + "float32x2_t vn", + "float32x2_t vm" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.2S" + }, + "vn": { + "register": "Vn.2S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMIN" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vaminq_f16", + "arguments": [ + "float16x8_t vn", + "float16x8_t vm" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.8H" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMIN" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vaminq_f32", + "arguments": [ + "float32x4_t vn", + "float32x4_t vm" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.4S" + }, + "vn": { + "register": "Vn.4S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMIN" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vaminq_f64", + "arguments": [ + "float64x2_t vn", + "float64x2_t vm" + ], + "return_type": { + "value": "float64x2_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.2D" + }, + "vn": { + "register": "Vn.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FAMIN" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vand_s16", @@ -5658,8 +208645,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -5685,8 +208676,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -5712,8 +208707,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -5739,8 +208738,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -5766,8 +208769,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -5793,8 +208800,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -5820,8 +208831,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -5847,8 +208862,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -7253,7 +210272,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.4H " + "register": "Vn.4H" }, "b": { "register": "Vm.4H" @@ -7281,7 +210300,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2S " + "register": "Vn.2S" }, "b": { "register": "Vm.2S" @@ -7309,7 +210328,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.4H " + "register": "Vn.4H" }, "b": { "register": "Vm.4H" @@ -7337,7 +210356,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2S " + "register": "Vn.2S" }, "b": { "register": "Vm.2S" @@ -7365,7 +210384,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.8H " + "register": "Vn.8H" }, "b": { "register": "Vm.8H" @@ -7393,7 +210412,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.4S " + "register": "Vn.4S" }, "b": { "register": "Vm.4S" @@ -7421,7 +210440,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2D " + "register": "Vn.2D" }, "b": { "register": "Vm.2D" @@ -7448,7 +210467,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.8H " + "register": "Vn.8H" }, "b": { "register": "Vm.8H" @@ -7476,7 +210495,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.4S " + "register": "Vn.4S" }, "b": { "register": "Vm.4S" @@ -7504,7 +210523,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2D " + "register": "Vn.2D" }, "b": { "register": "Vm.2D" @@ -15417,8 +218436,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + }, "r": { "register": "Vd.4H" } @@ -15445,8 +218468,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" + }, "r": { "register": "Vd.2S" } @@ -15474,8 +218501,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15507,8 +218538,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 0 @@ -15540,8 +218575,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15573,8 +218612,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15590,7 +218633,7 @@ "instructions": [ [ "DUP", - "FCMLA" + "" ] ] }, @@ -15606,8 +218649,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + }, "r": { "register": "Vd.4H" } @@ -15634,8 +218681,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" + }, "r": { "register": "Vd.2S" } @@ -15663,8 +218714,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15696,8 +218751,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 0 @@ -15729,8 +218788,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15762,8 +218825,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15779,7 +218846,7 @@ "instructions": [ [ "DUP", - "FCMLA" + "" ] ] }, @@ -15795,8 +218862,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + }, "r": { "register": "Vd.4H" } @@ -15823,8 +218894,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" + }, "r": { "register": "Vd.2S" } @@ -15852,8 +218927,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15885,8 +218964,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 0 @@ -15918,8 +219001,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15951,8 +219038,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 1 @@ -15968,7 +219059,7 @@ "instructions": [ [ "DUP", - "FCMLA" + "" ] ] }, @@ -15984,8 +219075,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + }, "r": { "register": "Vd.4H" } @@ -16012,8 +219107,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.2S" + }, "r": { "register": "Vd.2S" } @@ -16041,8 +219140,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16074,8 +219177,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 0 @@ -16107,8 +219214,12 @@ "value": "float16x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16140,8 +219251,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16157,7 +219272,7 @@ "instructions": [ [ "DUP", - "FCMLA" + "" ] ] }, @@ -16173,8 +219288,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + }, "r": { "register": "Vd.8H" } @@ -16201,8 +219320,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" + }, "r": { "register": "Vd.4S" } @@ -16229,8 +219352,12 @@ "value": "float64x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + }, "r": { "register": "Vd.2D" } @@ -16257,8 +219384,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16290,8 +219421,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 0 @@ -16323,8 +219458,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -16356,8 +219495,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16388,8 +219531,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + }, "r": { "register": "Vd.8H" } @@ -16416,8 +219563,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" + }, "r": { "register": "Vd.4S" } @@ -16444,8 +219595,12 @@ "value": "float64x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + }, "r": { "register": "Vd.2D" } @@ -16472,8 +219627,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16505,8 +219664,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 0 @@ -16538,8 +219701,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -16571,8 +219738,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16603,8 +219774,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + }, "r": { "register": "Vd.8H" } @@ -16631,8 +219806,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" + }, "r": { "register": "Vd.4S" } @@ -16659,8 +219838,12 @@ "value": "float64x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + }, "r": { "register": "Vd.2D" } @@ -16687,8 +219870,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16720,8 +219907,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 0 @@ -16753,8 +219944,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -16786,8 +219981,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16818,8 +220017,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + }, "r": { "register": "Vd.8H" } @@ -16846,8 +220049,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.4S" + }, "r": { "register": "Vd.4S" } @@ -16874,8 +220081,12 @@ "value": "float64x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.2D" + }, + "b": { + "register": "Vm.2D" + }, "r": { "register": "Vd.2D" } @@ -16902,8 +220113,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 1 @@ -16935,8 +220150,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 0 @@ -16968,8 +220187,12 @@ "value": "float16x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -17001,8 +220224,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vn.4S" + }, + "b": { + "register": "Vm.S" + }, "lane": { "minimum": 0, "maximum": 1 @@ -20921,7 +224148,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -20991,7 +224217,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -21933,7 +225158,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -22003,7 +225227,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -22261,7 +225484,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -22331,7 +225553,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -22777,7 +225998,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -22847,7 +226067,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -23293,7 +226512,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -23363,7 +226581,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -28161,8 +231378,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -28188,8 +231409,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -28215,8 +231440,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -28242,8 +231471,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -28269,8 +231502,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -28296,8 +231533,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -28323,8 +231564,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -28350,8 +231595,12 @@ "a": { "register": "Vn.16B" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.16B" + }, + "c": { + "register": "Va.16B" + } }, "Architectures": [ "A64" @@ -30097,7 +233346,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4H " + "register": "Vd.4H" }, "b": { "register": "Vn.4H" @@ -30680,7 +233929,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8H " + "register": "Vd.8H" }, "b": { "register": "Vn.8H" @@ -30846,8 +234095,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vd.2H" + }, "r": { "register": "Vd.2S" } @@ -30875,8 +234128,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -30908,8 +234165,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -30941,8 +234202,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -30974,8 +234239,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31006,8 +234275,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vd.2H" + }, "r": { "register": "Vd.2S" } @@ -31034,8 +234307,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vd.4H" + }, "r": { "register": "Vd.4S" } @@ -31063,8 +234340,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31096,8 +234377,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31129,8 +234414,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31162,8 +234451,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31194,8 +234487,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vd.4H" + }, "r": { "register": "Vd.4S" } @@ -31222,8 +234519,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vd.2H" + }, "r": { "register": "Vd.2S" } @@ -31251,8 +234552,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31284,8 +234589,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31317,8 +234626,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31350,8 +234663,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31382,8 +234699,12 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.2H" + }, + "b": { + "register": "Vd.2H" + }, "r": { "register": "Vd.2S" } @@ -31410,8 +234731,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vd.4H" + }, "r": { "register": "Vd.4S" } @@ -31439,8 +234764,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31472,8 +234801,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 3 @@ -31505,8 +234838,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31538,8 +234875,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vm.H" + }, "lane": { "minimum": 0, "maximum": 7 @@ -31570,8 +234911,12 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vd.4H" + }, "r": { "register": "Vd.4S" } @@ -31911,7 +235256,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.4H " + "register": "Vd.4H" }, "b": { "register": "Vn.4H" @@ -32492,7 +235837,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vd.8H " + "register": "Vd.8H" }, "b": { "register": "Vn.8H" @@ -34868,230 +238213,6 @@ ] ] }, - { - "SIMD_ISA": "Neon", - "name": "vldap1_lane_u64", - "arguments": [ - "uint64_t const * ptr", - "uint64x1_t src", - "const int lane" - ], - "return_type": { - "value": "uint64x1_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.1D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1_lane_s64", - "arguments": [ - "int64_t const * ptr", - "int64x1_t src", - "const int lane" - ], - "return_type": { - "value": "int64x1_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.1D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1q_lane_u64", - "arguments": [ - "uint64_t const * ptr", - "uint64x2_t src", - "const int lane" - ], - "return_type": { - "value": "uint64x2_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1q_lane_s64", - "arguments": [ - "int64_t const * ptr", - "int64x2_t src", - "const int lane" - ], - "return_type": { - "value": "int64x2_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1_lane_p64", - "arguments": [ - "poly64_t const * ptr", - "poly64x1_t src", - "const int lane" - ], - "return_type": { - "value": "poly64x1_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.1D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1q_lane_p64", - "arguments": [ - "poly64_t const * ptr", - "poly64x2_t src", - "const int lane" - ], - "return_type": { - "value": "poly64x2_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vldap1q_lane_f64", - "arguments": [ - "float64_t const * ptr", - "float64x2_t src", - "const int lane" - ], - "return_type": { - "value": "float64x2_t" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "src": { - "register": "Vt.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LDAP1" - ] - ] - }, { "SIMD_ISA": "Neon", "name": "vld1_dup_f16", @@ -39947,7 +243068,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { "register": "Vt2.4H" } }, @@ -39981,7 +243105,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { "register": "Vt2.2S" } }, @@ -40015,7 +243142,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { "register": "Vt2.1D" } }, @@ -40047,7 +243177,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { "register": "Vt2.4H" } }, @@ -40081,7 +243214,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { "register": "Vt2.1D" } }, @@ -40113,7 +243249,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { "register": "Vt2.8B" } }, @@ -40147,7 +243286,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { "register": "Vt2.4H" } }, @@ -40181,7 +243323,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { "register": "Vt2.2S" } }, @@ -40215,7 +243360,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { "register": "Vt2.1D" } }, @@ -40247,7 +243395,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { "register": "Vt2.8B" } }, @@ -40281,7 +243432,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { "register": "Vt2.4H" } }, @@ -40315,7 +243469,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { "register": "Vt2.2S" } }, @@ -40349,7 +243506,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { "register": "Vt2.1D" } }, @@ -40381,7 +243541,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { "register": "Vt2.8B" } }, @@ -41104,7 +244267,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { "register": "Vt2.8H" } }, @@ -41138,7 +244304,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { "register": "Vt2.4S" } }, @@ -41172,7 +244341,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { "register": "Vt2.2D" } }, @@ -41204,7 +244376,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { "register": "Vt2.8H" } }, @@ -41238,7 +244413,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { "register": "Vt2.2D" } }, @@ -41270,7 +244448,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { "register": "Vt2.16B" } }, @@ -41302,7 +244483,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { "register": "Vt2.8H" } }, @@ -41336,7 +244520,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { "register": "Vt2.4S" } }, @@ -41370,7 +244557,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { "register": "Vt2.2D" } }, @@ -41402,7 +244592,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { "register": "Vt2.16B" } }, @@ -41434,7 +244627,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { "register": "Vt2.8H" } }, @@ -41468,7 +244664,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { "register": "Vt2.4S" } }, @@ -41502,7 +244701,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { "register": "Vt2.2D" } }, @@ -41534,7 +244736,10 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { "register": "Vt2.16B" } }, @@ -42255,7 +245460,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { "register": "Vt3.4H" } }, @@ -42289,7 +245500,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { "register": "Vt3.2S" } }, @@ -42323,7 +245540,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { "register": "Vt3.1D" } }, @@ -42355,7 +245578,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { "register": "Vt3.4H" } }, @@ -42389,7 +245618,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { "register": "Vt3.1D" } }, @@ -42421,7 +245656,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { "register": "Vt3.8B" } }, @@ -42455,7 +245696,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { "register": "Vt3.4H" } }, @@ -42489,7 +245736,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { "register": "Vt3.2S" } }, @@ -42523,7 +245776,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { "register": "Vt3.1D" } }, @@ -42555,7 +245814,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { "register": "Vt3.8B" } }, @@ -42589,7 +245854,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { "register": "Vt3.4H" } }, @@ -42623,7 +245894,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { "register": "Vt3.2S" } }, @@ -42657,7 +245934,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { "register": "Vt3.1D" } }, @@ -42689,7 +245972,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { "register": "Vt3.8B" } }, @@ -43412,7 +246701,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { "register": "Vt3.8H" } }, @@ -43446,7 +246741,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { "register": "Vt3.4S" } }, @@ -43480,7 +246781,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { "register": "Vt3.2D" } }, @@ -43512,7 +246819,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { "register": "Vt3.8H" } }, @@ -43546,7 +246859,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { "register": "Vt3.2D" } }, @@ -43578,7 +246897,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { "register": "Vt3.16B" } }, @@ -43610,7 +246935,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { "register": "Vt3.8H" } }, @@ -43644,7 +246975,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { "register": "Vt3.4S" } }, @@ -43678,7 +247015,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { "register": "Vt3.2D" } }, @@ -43710,7 +247053,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { "register": "Vt3.16B" } }, @@ -43742,7 +247091,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { "register": "Vt3.8H" } }, @@ -43776,7 +247131,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { "register": "Vt3.4S" } }, @@ -43810,7 +247171,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { "register": "Vt3.2D" } }, @@ -43842,7 +247209,13 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { "register": "Vt3.16B" } }, @@ -44563,7 +247936,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" + }, + "src.val[3]": { "register": "Vt4.4H" } }, @@ -44597,7 +247979,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { + "register": "Vt3.2S" + }, + "src.val[3]": { "register": "Vt4.2S" } }, @@ -44631,7 +248022,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" + }, + "src.val[3]": { "register": "Vt4.1D" } }, @@ -44663,7 +248063,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" + }, + "src.val[3]": { "register": "Vt4.4H" } }, @@ -44697,7 +248106,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" + }, + "src.val[3]": { "register": "Vt4.1D" } }, @@ -44729,7 +248147,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { + "register": "Vt3.8B" + }, + "src.val[3]": { "register": "Vt4.8B" } }, @@ -44763,7 +248190,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" + }, + "src.val[3]": { "register": "Vt4.4H" } }, @@ -44797,7 +248233,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { + "register": "Vt3.2S" + }, + "src.val[3]": { "register": "Vt4.2S" } }, @@ -44831,7 +248276,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" + }, + "src.val[3]": { "register": "Vt4.1D" } }, @@ -44863,7 +248317,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { + "register": "Vt3.8B" + }, + "src.val[3]": { "register": "Vt4.8B" } }, @@ -44897,7 +248360,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4H" + }, + "src.val[1]": { + "register": "Vt2.4H" + }, + "src.val[2]": { + "register": "Vt3.4H" + }, + "src.val[3]": { "register": "Vt4.4H" } }, @@ -44931,7 +248403,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2S" + }, + "src.val[1]": { + "register": "Vt2.2S" + }, + "src.val[2]": { + "register": "Vt3.2S" + }, + "src.val[3]": { "register": "Vt4.2S" } }, @@ -44965,7 +248446,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.1D" + }, + "src.val[1]": { + "register": "Vt2.1D" + }, + "src.val[2]": { + "register": "Vt3.1D" + }, + "src.val[3]": { "register": "Vt4.1D" } }, @@ -44997,7 +248487,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8B" + }, + "src.val[1]": { + "register": "Vt2.8B" + }, + "src.val[2]": { + "register": "Vt3.8B" + }, + "src.val[3]": { "register": "Vt4.8B" } }, @@ -45720,7 +249219,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" + }, + "src.val[3]": { "register": "Vt4.8H" } }, @@ -45754,7 +249262,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { + "register": "Vt3.4S" + }, + "src.val[3]": { "register": "Vt4.4S" } }, @@ -45788,7 +249305,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" + }, + "src.val[3]": { "register": "Vt4.2D" } }, @@ -45820,7 +249346,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" + }, + "src.val[3]": { "register": "Vt4.8H" } }, @@ -45854,7 +249389,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" + }, + "src.val[3]": { "register": "Vt4.2D" } }, @@ -45886,7 +249430,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { + "register": "Vt3.16B" + }, + "src.val[3]": { "register": "Vt4.16B" } }, @@ -45918,7 +249471,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" + }, + "src.val[3]": { "register": "Vt4.8H" } }, @@ -45952,7 +249514,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { + "register": "Vt3.4S" + }, + "src.val[3]": { "register": "Vt4.4S" } }, @@ -45986,7 +249557,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" + }, + "src.val[3]": { "register": "Vt4.2D" } }, @@ -46018,7 +249598,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { + "register": "Vt3.16B" + }, + "src.val[3]": { "register": "Vt4.16B" } }, @@ -46050,7 +249639,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.8H" + }, + "src.val[1]": { + "register": "Vt2.8H" + }, + "src.val[2]": { + "register": "Vt3.8H" + }, + "src.val[3]": { "register": "Vt4.8H" } }, @@ -46084,7 +249682,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.4S" + }, + "src.val[1]": { + "register": "Vt2.4S" + }, + "src.val[2]": { + "register": "Vt3.4S" + }, + "src.val[3]": { "register": "Vt4.4S" } }, @@ -46118,7 +249725,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.2D" + }, + "src.val[1]": { + "register": "Vt2.2D" + }, + "src.val[2]": { + "register": "Vt3.2D" + }, + "src.val[3]": { "register": "Vt4.2D" } }, @@ -46150,7 +249766,16 @@ "ptr": { "register": "Xn" }, - "src": { + "src.val[0]": { + "register": "Vt.16B" + }, + "src.val[1]": { + "register": "Vt2.16B" + }, + "src.val[2]": { + "register": "Vt3.16B" + }, + "src.val[3]": { "register": "Vt4.16B" } }, @@ -46432,6 +250057,262 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vldap1_lane_f64", + "arguments": [ + "float64_t const * ptr", + "float64x1_t src", + "const int lane" + ], + "return_type": { + "value": "float64x1_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1_lane_p64", + "arguments": [ + "poly64_t const * ptr", + "poly64x1_t src", + "const int lane" + ], + "return_type": { + "value": "poly64x1_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1_lane_s64", + "arguments": [ + "int64_t const * ptr", + "int64x1_t src", + "const int lane" + ], + "return_type": { + "value": "int64x1_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1_lane_u64", + "arguments": [ + "uint64_t const * ptr", + "uint64x1_t src", + "const int lane" + ], + "return_type": { + "value": "uint64x1_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1q_lane_f64", + "arguments": [ + "float64_t const * ptr", + "float64x2_t src", + "const int lane" + ], + "return_type": { + "value": "float64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1q_lane_p64", + "arguments": [ + "poly64_t const * ptr", + "poly64x2_t src", + "const int lane" + ], + "return_type": { + "value": "poly64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1q_lane_s64", + "arguments": [ + "int64_t const * ptr", + "int64x2_t src", + "const int lane" + ], + "return_type": { + "value": "int64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vldap1q_lane_u64", + "arguments": [ + "uint64_t const * ptr", + "uint64x2_t src", + "const int lane" + ], + "return_type": { + "value": "uint64x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 1 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LDAP1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vldrq_p128", @@ -46456,6 +250337,1374 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_f16", + "arguments": [ + "float16x4_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_p16", + "arguments": [ + "poly16x4_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "poly16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_p8", + "arguments": [ + "poly8x8_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "poly8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_s16", + "arguments": [ + "int16x4_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_s8", + "arguments": [ + "int8x8_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "int8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_u16", + "arguments": [ + "uint16x4_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_lane_u8", + "arguments": [ + "uint8x8_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "uint8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_laneq_f16", + "arguments": [ + "float16x4_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 7 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_laneq_p16", + "arguments": [ + "poly16x4_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "poly16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 7 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_laneq_p8", + "arguments": [ + "poly8x8_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "poly8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_laneq_s16", + "arguments": [ + "int16x4_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 7 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_laneq_s8", + "arguments": [ + "int8x8_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "int8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_laneq_u16", + "arguments": [ + "uint16x4_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 7 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2_laneq_u8", + "arguments": [ + "uint8x8_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "uint8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_lane_f16", + "arguments": [ + "float16x8_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_lane_p16", + "arguments": [ + "poly16x8_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "poly16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_lane_p8", + "arguments": [ + "poly8x16_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "poly8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_lane_s16", + "arguments": [ + "int16x8_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_lane_s8", + "arguments": [ + "int8x16_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "int8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_lane_u16", + "arguments": [ + "uint16x8_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_lane_u8", + "arguments": [ + "uint8x16_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "uint8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_laneq_f16", + "arguments": [ + "float16x8_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 7 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_laneq_p16", + "arguments": [ + "poly16x8_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "poly16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 7 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_laneq_p8", + "arguments": [ + "poly8x16_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "poly8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_laneq_s16", + "arguments": [ + "int16x8_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 7 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_laneq_s8", + "arguments": [ + "int8x16_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "int8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_laneq_u16", + "arguments": [ + "uint16x8_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 7 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti2q_laneq_u8", + "arguments": [ + "uint8x16_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "uint8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti4q_lane_f16_x2", + "arguments": [ + "float16x8x2_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti4q_lane_p16_x2", + "arguments": [ + "poly16x8x2_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "poly16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti4q_lane_p8", + "arguments": [ + "poly8x16_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "poly8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 0 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti4q_lane_s16_x2", + "arguments": [ + "int16x8x2_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti4q_lane_s8", + "arguments": [ + "int8x16_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "int8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 0 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti4q_lane_u16_x2", + "arguments": [ + "uint16x8x2_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti4q_lane_u8", + "arguments": [ + "uint8x16_t vn", + "uint8x8_t vm", + "const int index" + ], + "return_type": { + "value": "uint8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 0 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti4q_laneq_f16_x2", + "arguments": [ + "float16x8x2_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti4q_laneq_p16_x2", + "arguments": [ + "poly16x8x2_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "poly16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti4q_laneq_p8", + "arguments": [ + "poly8x16_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "poly8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti4q_laneq_s16_x2", + "arguments": [ + "int16x8x2_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti4q_laneq_s8", + "arguments": [ + "int8x16_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "int8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti4q_laneq_u16_x2", + "arguments": [ + "uint16x8x2_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 3 + }, + "vm": { + "register": "Vm" + }, + "vn.val[0]": { + "register": "Vn1.8H" + }, + "vn.val[1]": { + "register": "Vn2.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI4" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vluti4q_laneq_u8", + "arguments": [ + "uint8x16_t vn", + "uint8x16_t vm", + "const int index" + ], + "return_type": { + "value": "uint8x16_t" + }, + "Arguments_Preparation": { + "index": { + "minimum": 0, + "maximum": 1 + }, + "vm": { + "register": "Vm" + }, + "vn": { + "register": "Vn.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "LUTI4" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmax_f16", @@ -47388,7 +252637,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vm.2S" } }, "Architectures": [ @@ -47457,7 +252706,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vm.2S" } }, "Architectures": [ @@ -48631,7 +253880,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vm.2S" } }, "Architectures": [ @@ -48700,7 +253949,7 @@ }, "Arguments_Preparation": { "a": { - "register": "Vn.2S" + "register": "Vm.2S" } }, "Architectures": [ @@ -48971,7 +254220,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -49002,7 +254251,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -49019,13 +254268,10 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 1 - }, - "v": {} + } }, "Architectures": [ "v7", @@ -49034,7 +254280,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -49203,20 +254449,17 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 3 - }, - "v": {} + } }, "Architectures": [ "A64" ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -49393,7 +254636,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -50980,7 +256223,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -51011,7 +256254,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -51028,13 +256271,10 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 1 - }, - "v": {} + } }, "Architectures": [ "v7", @@ -51043,7 +256283,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -51212,20 +256452,17 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 3 - }, - "v": {} + } }, "Architectures": [ "A64" ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -51402,7 +256639,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -51765,7 +257002,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -51796,7 +257033,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -51813,13 +257050,10 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 1 - }, - "v": {} + } }, "Architectures": [ "v7", @@ -51828,7 +257062,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -51997,20 +257231,17 @@ "value": "float32x2_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 3 - }, - "v": {} + } }, "Architectures": [ "A64" ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -52187,7 +257418,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -53774,7 +259005,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -53805,7 +259036,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -53822,13 +259053,10 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 1 - }, - "v": {} + } }, "Architectures": [ "v7", @@ -53837,7 +259065,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -54006,20 +259234,17 @@ "value": "float32x4_t" }, "Arguments_Preparation": { - "a": {}, - "b": {}, "lane": { "minimum": 0, "maximum": 3 - }, - "v": {} + } }, "Architectures": [ "A64" ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -54196,7 +259421,7 @@ ], "instructions": [ [ - "RESULT[I]" + "result" ] ] }, @@ -75953,8 +281178,11 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -75980,8 +281208,11 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76007,8 +281238,11 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76034,8 +281268,11 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76061,8 +281298,11 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76088,8 +281328,11 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76115,8 +281358,14 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76142,8 +281391,14 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76169,8 +281424,14 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76196,8 +281457,14 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76223,8 +281490,14 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76250,8 +281523,14 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76277,8 +281556,17 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -76304,8 +281592,17 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -76331,8 +281628,17 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -76358,8 +281664,17 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -76385,8 +281700,17 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -76412,8 +281736,17 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -76629,8 +281962,11 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76660,8 +281996,11 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76691,8 +282030,11 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76722,8 +282064,11 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76753,8 +282098,11 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76784,8 +282132,11 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" } }, "Architectures": [ @@ -76815,8 +282166,14 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76846,8 +282203,14 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76877,8 +282240,14 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76908,8 +282277,14 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76939,8 +282314,14 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -76970,8 +282351,14 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" } }, "Architectures": [ @@ -77001,8 +282388,17 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -77032,8 +282428,17 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -77063,8 +282468,17 @@ "idx": { "register": "Vm.8B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -77094,8 +282508,17 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -77125,8 +282548,17 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -77156,8 +282588,17 @@ "idx": { "register": "Vm.16B" }, - "t": { + "t.val[0]": { "register": "Vn.16B" + }, + "t.val[1]": { + "register": "Vn+1.16B" + }, + "t.val[2]": { + "register": "Vn+2.16B" + }, + "t.val[3]": { + "register": "Vn+3.16B" } }, "Architectures": [ @@ -77543,7 +282984,9 @@ "a": { "register": "Vn.2D" }, - "b": {} + "b": { + "register": "Vm.2D" + } }, "Architectures": [ "A64" @@ -93507,6 +298950,141 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vscale_f16", + "arguments": [ + "float16x4_t vn", + "int16x4_t vm" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.4H" + }, + "vn": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscale_f32", + "arguments": [ + "float32x2_t vn", + "int32x2_t vm" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.2S" + }, + "vn": { + "register": "Vn.2S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscaleq_f16", + "arguments": [ + "float16x8_t vn", + "int16x8_t vm" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.8H" + }, + "vn": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscaleq_f32", + "arguments": [ + "float32x4_t vn", + "int32x4_t vm" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.4S" + }, + "vn": { + "register": "Vn.4S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vscaleq_f64", + "arguments": [ + "float64x2_t vn", + "int64x2_t vm" + ], + "return_type": { + "value": "float64x2_t" + }, + "Arguments_Preparation": { + "vm": { + "register": "Vm.2D" + }, + "vn": { + "register": "Vn.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSCALE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vset_lane_f16", @@ -94769,7 +300347,9 @@ "value": "uint64x2_t" }, "Arguments_Preparation": { - "hash_ab": {}, + "hash_ab": { + "register": "Vm.2D" + }, "hash_c_": { "register": "Qn" }, @@ -94804,7 +300384,9 @@ "hash_gf": { "register": "Qn" }, - "kwh_kwh2": {} + "kwh_kwh2": { + "register": "Vm.2D" + } }, "Architectures": [ "A64" @@ -94860,7 +300442,9 @@ "w14_15": { "register": "Vn.2D" }, - "w9_10": {} + "w9_10": { + "register": "Vm.2D" + } }, "Architectures": [ "A64" @@ -98006,8 +303590,12 @@ "a": { "register": "Vd.4S" }, - "b": {}, - "c": {} + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" + } }, "Architectures": [ "A64" @@ -98033,8 +303621,12 @@ "a": { "register": "Vd.4S" }, - "b": {}, - "c": {} + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" + } }, "Architectures": [ "A64" @@ -98060,8 +303652,12 @@ "a": { "register": "Vn.4S" }, - "b": {}, - "c": {} + "b": { + "register": "Vm.4S" + }, + "c": { + "register": "Va.4S" + } }, "Architectures": [ "A64" @@ -98088,8 +303684,12 @@ "a": { "register": "Vd.4S" }, - "b": {}, - "c": {}, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" + }, "imm2": { "minimum": 0, "maximum": 3 @@ -98120,8 +303720,12 @@ "a": { "register": "Vd.4S" }, - "b": {}, - "c": {}, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" + }, "imm2": { "minimum": 0, "maximum": 3 @@ -98152,8 +303756,12 @@ "a": { "register": "Vd.4S" }, - "b": {}, - "c": {}, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" + }, "imm2": { "minimum": 0, "maximum": 3 @@ -98184,8 +303792,12 @@ "a": { "register": "Vd.4S" }, - "b": {}, - "c": {}, + "b": { + "register": "Vn.4S" + }, + "c": { + "register": "Vm.4S" + }, "imm2": { "minimum": 0, "maximum": 3 @@ -98214,7 +303826,9 @@ "a": { "register": "Vn.4S" }, - "b": {} + "b": { + "register": "Vm.4S" + } }, "Architectures": [ "A64" @@ -98239,7 +303853,9 @@ "a": { "register": "Vd.4S" }, - "b": {} + "b": { + "register": "Vn.4S" + } }, "Architectures": [ "A64" @@ -100197,7 +305813,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -100226,7 +305845,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -100255,7 +305880,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -100313,7 +305947,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -100342,7 +305979,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -100371,7 +306014,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -100427,7 +306079,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -100454,7 +306109,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -100481,7 +306142,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -100967,6 +306637,42 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst1_mf8_x4", + "arguments": [ + "int8_t * ptr", + "int8x8x4_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { + "register": "Vt4.8B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst1_p16", @@ -101010,7 +306716,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -101039,7 +306748,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -101068,7 +306783,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -101125,7 +306849,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -101153,7 +306880,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -101181,7 +306914,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -101238,7 +306980,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -101267,7 +307012,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -101296,7 +307047,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -101354,7 +307114,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -101383,7 +307146,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -101412,7 +307181,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -101470,7 +307248,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -101499,7 +307280,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -101528,7 +307315,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -101586,7 +307382,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -101615,7 +307414,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -101644,7 +307449,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -101702,7 +307516,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -101731,7 +307548,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -101760,7 +307583,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -101818,7 +307650,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -101847,7 +307682,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -101876,7 +307717,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -101934,7 +307784,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -101963,7 +307816,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -101992,7 +307851,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -102050,7 +307918,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -102079,7 +307950,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -102108,7 +307985,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -102166,7 +308052,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -102195,7 +308084,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -102224,7 +308119,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -102282,7 +308186,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -102311,7 +308218,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -102340,7 +308253,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -102398,7 +308320,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -102427,7 +308352,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -102456,7 +308387,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -102512,7 +308452,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -102539,7 +308482,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -102566,7 +308515,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -103052,6 +309010,42 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst1q_mf8_x4", + "arguments": [ + "int8_t * ptr", + "int8x16x4_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { + "register": "Vt4.16B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ST1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst1q_p16", @@ -103095,7 +309089,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -103124,7 +309121,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -103153,7 +309156,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -103210,7 +309222,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -103238,7 +309253,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -103267,7 +309288,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -103324,7 +309354,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -103353,7 +309386,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -103382,7 +309421,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -103440,7 +309488,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -103469,7 +309520,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -103498,7 +309555,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -103556,7 +309622,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -103585,7 +309654,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -103614,7 +309689,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -103672,7 +309756,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -103701,7 +309788,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -103730,7 +309823,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -103788,7 +309890,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -103817,7 +309922,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -103846,7 +309957,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -103904,7 +310024,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -103933,7 +310056,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -103962,7 +310091,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -104020,7 +310158,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -104049,7 +310190,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -104078,7 +310225,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -104136,7 +310292,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -104165,7 +310324,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -104194,7 +310359,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -104252,7 +310426,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -104281,7 +310458,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -104310,7 +310493,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -104339,7 +310531,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -104368,7 +310563,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -104397,7 +310595,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -104429,7 +310630,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -104463,7 +310667,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -104497,7 +310704,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -104529,7 +310739,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -104563,7 +310776,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -104595,7 +310811,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -104629,7 +310848,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -104663,7 +310885,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -104697,7 +310922,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -104729,7 +310957,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -104763,7 +310994,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -104797,7 +311031,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -104831,7 +311068,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -104863,7 +311103,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -104892,7 +311135,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -104921,7 +311167,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -104949,7 +311198,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -104978,7 +311230,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -105007,7 +311262,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -105036,7 +311294,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -105065,7 +311326,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -105094,7 +311358,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { "register": "Vt2.4H" } }, @@ -105123,7 +311390,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { "register": "Vt2.2S" } }, @@ -105152,7 +311422,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { "register": "Vt2.1D" } }, @@ -105181,7 +311454,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { "register": "Vt2.8B" } }, @@ -105210,7 +311486,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105239,7 +311518,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -105268,7 +311550,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -105300,7 +311585,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105334,7 +311622,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -105363,12 +311654,15 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 2 + "maximum": 1 }, "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -105400,7 +311694,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105434,7 +311731,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -105466,7 +311766,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -105498,7 +311801,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105532,7 +311838,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -105566,7 +311875,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -105598,7 +311910,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -105630,7 +311945,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105664,7 +311982,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -105698,7 +312019,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -105730,7 +312054,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -105757,7 +312084,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105786,7 +312116,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -105813,7 +312146,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -105842,7 +312178,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105871,7 +312210,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -105900,7 +312242,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -105927,7 +312272,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -105956,7 +312304,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { "register": "Vt2.8H" } }, @@ -105985,7 +312336,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { "register": "Vt2.4S" } }, @@ -106014,7 +312368,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { "register": "Vt2.2D" } }, @@ -106041,7 +312398,10 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { "register": "Vt2.16B" } }, @@ -106070,7 +312430,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -106099,7 +312465,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -106128,7 +312500,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -106160,7 +312538,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -106194,7 +312578,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -106228,7 +312618,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -106260,7 +312656,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -106294,7 +312696,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -106326,7 +312734,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -106360,7 +312774,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -106394,7 +312814,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -106428,7 +312854,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -106460,7 +312892,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -106494,7 +312932,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -106528,7 +312972,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -106562,7 +313012,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -106594,7 +313050,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -106623,7 +313085,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -106652,7 +313120,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -106680,7 +313154,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -106709,7 +313189,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -106738,7 +313224,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -106767,7 +313259,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -106796,7 +313294,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -106825,7 +313329,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { "register": "Vt3.4H" } }, @@ -106854,7 +313364,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { "register": "Vt3.2S" } }, @@ -106883,7 +313399,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { "register": "Vt3.1D" } }, @@ -106912,7 +313434,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { "register": "Vt3.8B" } }, @@ -106941,7 +313469,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -106970,7 +313504,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -106999,7 +313539,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -107031,7 +313577,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -107065,7 +313617,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -107099,7 +313657,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -107131,7 +313695,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -107165,7 +313735,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -107197,7 +313773,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -107231,7 +313813,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -107265,7 +313853,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -107299,7 +313893,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -107331,7 +313931,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -107365,7 +313971,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -107399,7 +314011,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -107433,7 +314051,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -107465,7 +314089,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -107494,7 +314124,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -107523,7 +314159,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -107550,7 +314192,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -107579,7 +314227,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -107608,7 +314262,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -107637,7 +314297,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -107664,7 +314330,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -107693,7 +314365,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { "register": "Vt3.8H" } }, @@ -107722,7 +314400,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { "register": "Vt3.4S" } }, @@ -107751,7 +314435,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { "register": "Vt3.2D" } }, @@ -107778,7 +314468,13 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { "register": "Vt3.16B" } }, @@ -107807,7 +314503,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -107836,7 +314541,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -107865,7 +314579,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -107897,7 +314620,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -107931,7 +314663,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -107965,7 +314706,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -107997,7 +314747,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -108031,7 +314790,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -108063,7 +314831,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -108097,7 +314874,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -108131,7 +314917,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -108165,7 +314960,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -108197,7 +315001,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -108231,7 +315044,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -108265,7 +315087,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -108299,7 +315130,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -108331,7 +315171,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -108360,7 +315209,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -108389,7 +315247,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -108417,7 +315284,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -108446,7 +315322,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -108475,7 +315360,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -108504,7 +315398,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -108533,7 +315436,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -108562,7 +315474,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4H" + }, + "val.val[1]": { + "register": "Vt2.4H" + }, + "val.val[2]": { + "register": "Vt3.4H" + }, + "val.val[3]": { "register": "Vt4.4H" } }, @@ -108591,7 +315512,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2S" + }, + "val.val[1]": { + "register": "Vt2.2S" + }, + "val.val[2]": { + "register": "Vt3.2S" + }, + "val.val[3]": { "register": "Vt4.2S" } }, @@ -108620,7 +315550,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.1D" + }, + "val.val[1]": { + "register": "Vt2.1D" + }, + "val.val[2]": { + "register": "Vt3.1D" + }, + "val.val[3]": { "register": "Vt4.1D" } }, @@ -108649,7 +315588,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8B" + }, + "val.val[1]": { + "register": "Vt2.8B" + }, + "val.val[2]": { + "register": "Vt3.8B" + }, + "val.val[3]": { "register": "Vt4.8B" } }, @@ -108678,7 +315626,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -108707,7 +315664,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -108736,7 +315702,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -108768,7 +315743,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -108802,7 +315786,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -108836,7 +315829,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -108868,7 +315870,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -108902,7 +315913,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -108934,7 +315954,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -108966,7 +315995,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -109000,7 +316038,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -109034,7 +316081,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -109066,7 +316122,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -109098,7 +316163,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -109132,7 +316206,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -109166,7 +316249,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -109198,7 +316290,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -109225,7 +316326,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -109254,7 +316364,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -109281,7 +316400,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -109310,7 +316438,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -109339,7 +316476,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -109368,7 +316514,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -109395,7 +316550,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -109424,7 +316588,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.8H" + }, + "val.val[1]": { + "register": "Vt2.8H" + }, + "val.val[2]": { + "register": "Vt3.8H" + }, + "val.val[3]": { "register": "Vt4.8H" } }, @@ -109453,7 +316626,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.4S" + }, + "val.val[1]": { + "register": "Vt2.4S" + }, + "val.val[2]": { + "register": "Vt3.4S" + }, + "val.val[3]": { "register": "Vt4.4S" } }, @@ -109482,7 +316664,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.2D" + }, + "val.val[1]": { + "register": "Vt2.2D" + }, + "val.val[2]": { + "register": "Vt3.2D" + }, + "val.val[3]": { "register": "Vt4.2D" } }, @@ -109509,7 +316700,16 @@ "ptr": { "register": "Xn" }, - "val": { + "val.val[0]": { + "register": "Vt.16B" + }, + "val.val[1]": { + "register": "Vt2.16B" + }, + "val.val[2]": { + "register": "Vt3.16B" + }, + "val.val[3]": { "register": "Vt4.16B" } }, @@ -109526,38 +316726,106 @@ }, { "SIMD_ISA": "Neon", - "name": "vstrq_p128", + "name": "vstl1_lane_f64", "arguments": [ - "poly128_t * ptr", - "poly128_t val" + "float64_t * ptr", + "float64x1_t val", + "const int lane" ], "return_type": { "value": "void" }, "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, "ptr": { "register": "Xn" }, "val": { - "register": "Qt" + "register": "Vt.1D" } }, "Architectures": [ - "A32", "A64" ], "instructions": [ [ - "STR" + "STL1" ] ] }, { "SIMD_ISA": "Neon", - "name": "vstl1_lane_f64", + "name": "vstl1_lane_p64", "arguments": [ - "float64_t * ptr", - "float64x1_t val", + "poly64_t * ptr", + "poly64x1_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1_lane_s64", + "arguments": [ + "int64_t * ptr", + "int64x1_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 0 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "STL1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vstl1_lane_u64", + "arguments": [ + "uint64_t * ptr", + "uint64x1_t val", "const int lane" ], "return_type": { @@ -109616,38 +316884,6 @@ ] ] }, - { - "SIMD_ISA": "Neon", - "name": "vstl1_lane_p64", - "arguments": [ - "poly64_t * ptr", - "poly64x1_t val", - "const int lane" - ], - "return_type": { - "value": "void" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt.1D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "STL1" - ] - ] - }, { "SIMD_ISA": "Neon", "name": "vstl1q_lane_p64", @@ -109682,10 +316918,10 @@ }, { "SIMD_ISA": "Neon", - "name": "vstl1_lane_u64", + "name": "vstl1q_lane_s64", "arguments": [ - "uint64_t * ptr", - "uint64x1_t val", + "int64_t * ptr", + "int64x2_t val", "const int lane" ], "return_type": { @@ -109694,13 +316930,13 @@ "Arguments_Preparation": { "lane": { "minimum": 0, - "maximum": 0 + "maximum": 1 }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.1D" + "register": "Vt.2D" } }, "Architectures": [ @@ -109746,65 +316982,29 @@ }, { "SIMD_ISA": "Neon", - "name": "vstl1_lane_s64", + "name": "vstrq_p128", "arguments": [ - "int64_t * ptr", - "int64x1_t val", - "const int lane" + "poly128_t * ptr", + "poly128_t val" ], "return_type": { "value": "void" }, "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 0 - }, "ptr": { "register": "Xn" }, "val": { - "register": "Vt.1D" + "register": "Qt" } }, "Architectures": [ + "A32", "A64" ], "instructions": [ [ - "STL1" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vstl1q_lane_s64", - "arguments": [ - "int64_t * ptr", - "int64x2_t val", - "const int lane" - ], - "return_type": { - "value": "void" - }, - "Arguments_Preparation": { - "lane": { - "minimum": 0, - "maximum": 1 - }, - "ptr": { - "register": "Xn" - }, - "val": { - "register": "Vt.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "STL1" + "STR" ] ] }, @@ -111655,7 +318855,6 @@ } }, "Architectures": [ - "A32", "A64" ], "instructions": [ @@ -111711,10 +318910,12 @@ "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { + "Zeros(64):a": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111738,10 +318939,12 @@ "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { + "Zeros(64):a": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111765,10 +318968,12 @@ "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { + "Zeros(64):a": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111792,10 +318997,12 @@ "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111819,10 +319026,12 @@ "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111846,10 +319055,12 @@ "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111873,10 +319084,15 @@ "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { + "Zeros(64):a.val[2]": { + "register": "Vn+1.16B" + }, + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111900,10 +319116,15 @@ "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { + "Zeros(64):a.val[2]": { + "register": "Vn+1.16B" + }, + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111927,10 +319148,15 @@ "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { + "Zeros(64):a.val[2]": { + "register": "Vn+1.16B" + }, + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111954,10 +319180,15 @@ "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": { + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "a.val[3]:a.val[2]": { + "register": "Vn+1.16B" + }, + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -111981,10 +319212,15 @@ "value": "int8x8_t" }, "Arguments_Preparation": { - "a": { + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "a.val[3]:a.val[2]": { + "register": "Vn+1.16B" + }, + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112008,10 +319244,15 @@ "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": { + "a.val[1]:a.val[0]": { "register": "Vn.16B" }, - "idx": {} + "a.val[3]:a.val[2]": { + "register": "Vn+1.16B" + }, + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112036,11 +319277,15 @@ "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "Zeros(64):b": { "register": "Vn.16B" }, - "idx": {} + "a": { + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112068,11 +319313,15 @@ "value": "int8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "Zeros(64):b": { "register": "Vn.16B" }, - "idx": {} + "a": { + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112100,11 +319349,15 @@ "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "Zeros(64):b": { "register": "Vn.16B" }, - "idx": {} + "a": { + "register": "Vd.8B" + }, + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112132,11 +319385,15 @@ "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112161,11 +319418,15 @@ "value": "int8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112190,11 +319451,15 @@ "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112219,11 +319484,18 @@ "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "Zeros(64):b.val[2]": { + "register": "Vn+1.16B" + }, + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112251,11 +319523,18 @@ "value": "int8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "Zeros(64):b.val[2]": { + "register": "Vn+1.16B" + }, + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112283,11 +319562,18 @@ "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "Zeros(64):b.val[2]": { + "register": "Vn+1.16B" + }, + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "idx": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112315,11 +319601,18 @@ "value": "poly8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "b.val[3]:b.val[2]": { + "register": "Vn+1.16B" + }, + "c": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112344,11 +319637,18 @@ "value": "int8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "b.val[3]:b.val[2]": { + "register": "Vn+1.16B" + }, + "c": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -112373,11 +319673,18 @@ "value": "uint8x8_t" }, "Arguments_Preparation": { - "a": {}, - "b": { + "a": { + "register": "Vd.8B" + }, + "b.val[1]:b.val[0]": { "register": "Vn.16B" }, - "idx": {} + "b.val[3]:b.val[2]": { + "register": "Vn+1.16B" + }, + "c": { + "register": "Vm.8B" + } }, "Architectures": [ "v7", @@ -115435,6 +322742,7 @@ } }, "Architectures": [ + "A32", "A64" ], "instructions": [ @@ -117386,7 +324694,9 @@ "a": { "register": "Vn.2D" }, - "b": {}, + "b": { + "register": "Vm.2D" + }, "imm6": { "minimum": 0, "maximum": 63 @@ -119297,1746 +326607,6 @@ ] ] }, - { - "SIMD_ISA": "Neon", - "name": "vamin_f16", - "arguments": [ - "float16x4_t a", - "float16x4_t b" - ], - "return_type": { - "value": "float16x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "FAMIN" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vaminq_f16", - "arguments": [ - "float16x8_t a", - "float16x8_t b" - ], - "return_type": { - "value": "float16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "FAMIN" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vamin_f32", - "arguments": [ - "float32x2_t a", - "float32x2_t b" - ], - "return_type": { - "value": "float32x2_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "FAMIN" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vaminq_f32", - "arguments": [ - "float32x4_t a", - "float32x4_t b" - ], - "return_type": { - "value": "float32x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "FAMIN" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vaminq_f64", - "arguments": [ - "float64x2_t a", - "float64x2_t b" - ], - "return_type": { - "value": "float64x2_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "FAMIN" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vamax_f16", - "arguments": [ - "float16x4_t a", - "float16x4_t b" - ], - "return_type": { - "value": "float16x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.4H" - }, - "b": { - "register": "Vm.4H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "FAMAX" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vamaxq_f16", - "arguments": [ - "float16x8_t a", - "float16x8_t b" - ], - "return_type": { - "value": "float16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "FAMAX" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vamax_f32", - "arguments": [ - "float32x2_t a", - "float32x2_t b" - ], - "return_type": { - "value": "float32x2_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.2S" - }, - "b": { - "register": "Vm.2S" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "FAMAX" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vamaxq_f32", - "arguments": [ - "float32x4_t a", - "float32x4_t b" - ], - "return_type": { - "value": "float32x4_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.4S" - }, - "b": { - "register": "Vm.4S" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "FAMAX" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vamaxq_f64", - "arguments": [ - "float64x2_t a", - "float64x2_t b" - ], - "return_type": { - "value": "float64x2_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.2D" - }, - "b": { - "register": "Vm.2D" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "FAMAX" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2_lane_f16", - "arguments": [ - "float16x4_t a", - "uint8x8_t b", - "const int index" - ], - "return_type": { - "value": "float16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2_lane_s16", - "arguments": [ - "int16x4_t a", - "uint8x8_t b", - "const int index" - ], - "return_type": { - "value": "int16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2_lane_u16", - "arguments": [ - "uint16x4_t a", - "uint8x8_t b", - "const int index" - ], - "return_type": { - "value": "uint16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm" - }, - "lane": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2_lane_p16", - "arguments": [ - "poly16x4_t a", - "uint8x8_t b", - "const int index" - ], - "return_type": { - "value": "poly16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2_laneq_f16", - "arguments": [ - "float16x4_t a", - "uint8x16_t b", - "const int index" - ], - "return_type": { - "value": "float16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2_laneq_s16", - "arguments": [ - "int16x4_t a", - "uint8x16_t b", - "const int index" - ], - "return_type": { - "value": "int16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2_laneq_u16", - "arguments": [ - "uint16x4_t a", - "uint8x16_t b", - "const int index" - ], - "return_type": { - "value": "uint16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2_laneq_p16", - "arguments": [ - "poly16x4_t a", - "uint8x16_t b", - "const int index" - ], - "return_type": { - "value": "poly16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2q_lane_f16", - "arguments": [ - "float16x8_t a", - "uint8x8_t b", - "const int index" - ], - "return_type": { - "value": "float16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2q_lane_s16", - "arguments": [ - "int16x8_t a", - "uint8x8_t b", - "const int index" - ], - "return_type": { - "value": "int16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2q_lane_u16", - "arguments": [ - "uint16x8_t a", - "uint8x8_t b", - "const int index" - ], - "return_type": { - "value": "uint16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2q_lane_p16", - "arguments": [ - "poly16x8_t a", - "uint8x8_t b", - "const int index" - ], - "return_type": { - "value": "poly16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_f16", - "arguments": [ - "float16x8_t a", - "uint8x16_t b", - "const int index" - ], - "return_type": { - "value": "float16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_s16", - "arguments": [ - "int16x8_t a", - "uint8x16_t b", - "const int index" - ], - "return_type": { - "value": "int16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_u16", - "arguments": [ - "uint16x8_t a", - "uint8x16_t b", - "const int index" - ], - "return_type": { - "value": "uint16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2_lane_u8", - "arguments": [ - "uint8x8_t a", - "uint8x8_t b", - "const int lane" - ], - "return_type": { - "value": "uint8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2q_lane_u8", - "arguments": [ - "uint8x16_t a", - "uint8x8_t b", - "const int lane" - ], - "return_type": { - "value": "uint8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2_lane_s8", - "arguments": [ - "int8x8_t a", - "uint8x8_t b", - "const int lane" - ], - "return_type": { - "value": "int8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2q_lane_s8", - "arguments": [ - "int8x16_t a", - "uint8x8_t b", - "const int lane" - ], - "return_type": { - "value": "int8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2_lane_p8", - "arguments": [ - "poly8x8_t a", - "uint8x8_t b", - "const int lane" - ], - "return_type": { - "value": "poly8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2q_lane_p8", - "arguments": [ - "poly8x16_t a", - "uint8x8_t b", - "const int lane" - ], - "return_type": { - "value": "poly8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2_laneq_u8", - "arguments": [ - "uint8x8_t a", - "uint8x16_t b", - "const int index" - ], - "return_type": { - "value": "uint8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_u8", - "arguments": [ - "uint8x16_t a", - "uint8x16_t b", - "const int index" - ], - "return_type": { - "value": "uint8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2_laneq_s8", - "arguments": [ - "int8x8_t a", - "uint8x16_t b", - "const int index" - ], - "return_type": { - "value": "int8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_s8", - "arguments": [ - "int8x16_t a", - "uint8x16_t b", - "const int index" - ], - "return_type": { - "value": "int8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2_laneq_p8", - "arguments": [ - "poly8x8_t a", - "uint8x16_t b", - "const int index" - ], - "return_type": { - "value": "poly8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_p8", - "arguments": [ - "poly8x16_t a", - "uint8x16_t b", - "const int index" - ], - "return_type": { - "value": "poly8x16_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.16B" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti2q_laneq_p16", - "arguments": [ - "poly16x8_t a", - "uint8x16_t b", - "const int index" - ], - "return_type": { - "value": "poly16x8_t" - }, - "Arguments_Preparation": { - "a": { - "register": "Vn.8H" - }, - "b": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 7 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI2" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti4q_lane_u8", - "arguments": [ - "uint8x16_t vn", - "uint8x8_t vm", - "const int index" - ], - "return_type": { - "value": "uint8x16_t" - }, - "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 0 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_u8", - "arguments": [ - "uint8x16_t vn", - "uint8x16_t vm", - "const int index" - ], - "return_type": { - "value": "uint8x16_t" - }, - "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti4q_lane_s8", - "arguments": [ - "int8x16_t vn", - "uint8x8_t vm", - "const int index" - ], - "return_type": { - "value": "int8x16_t" - }, - "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 0 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_s8", - "arguments": [ - "int8x16_t vn", - "uint8x16_t vm", - "const int index" - ], - "return_type": { - "value": "int8x16_t" - }, - "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti4q_lane_p8", - "arguments": [ - "poly8x16_t vn", - "uint8x8_t vm", - "const int index" - ], - "return_type": { - "value": "poly8x16_t" - }, - "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 0 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_p8", - "arguments": [ - "poly8x16_t vn", - "uint8x16_t vm", - "const int index" - ], - "return_type": { - "value": "poly8x16_t" - }, - "Arguments_Preparation": { - "vn": { - "register": "Vn.16B" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.16B" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti4q_lane_u16_x2", - "arguments": [ - "uint16x8x2_t vn", - "uint8x8_t vm", - "const int index" - ], - "return_type": { - "value": "uint16x8_t" - }, - "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_u16_x2", - "arguments": [ - "uint16x8x2_t vn", - "uint8x16_t vm", - "const int index" - ], - "return_type": { - "value": "uint16x8_t" - }, - "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti4q_lane_s16_x2", - "arguments": [ - "int16x8x2_t vn", - "uint8x8_t vm", - "const int index" - ], - "return_type": { - "value": "int16x8_t" - }, - "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_s16_x2", - "arguments": [ - "int16x8x2_t vn", - "uint8x16_t vm", - "const int index" - ], - "return_type": { - "value": "int16x8_t" - }, - "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti4q_lane_f16_x2", - "arguments": [ - "float16x8x2_t vn", - "uint8x8_t vm", - "const int index" - ], - "return_type": { - "value": "float16x8_t" - }, - "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_f16_x2", - "arguments": [ - "float16x8x2_t vn", - "uint8x16_t vm", - "const int index" - ], - "return_type": { - "value": "float16x8_t" - }, - "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti4q_lane_p16_x2", - "arguments": [ - "poly16x8x2_t vn", - "uint8x8_t vm", - "const int index" - ], - "return_type": { - "value": "poly16x8_t" - }, - "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 1 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI4" - ] - ] - }, - { - "SIMD_ISA": "Neon", - "name": "vluti4q_laneq_p16_x2", - "arguments": [ - "poly16x8x2_t vn", - "uint8x16_t vm", - "const int index" - ], - "return_type": { - "value": "poly16x8_t" - }, - "Arguments_Preparation": { - "vn": { - "register": "Vn1.8H" - }, - "vm": { - "register": "Vm" - }, - "index": { - "minimum": 0, - "maximum": 3 - }, - "r": { - "register": "Vd.8H" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "LUTI4" - ] - ] - }, { "SIMD_ISA": "Neon", "name": "__jcvt",